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PRELIMINARY
Am186 EM/EMLV and Am188 EM/EMLV
TM TM
High Performance, 80C186-/80C188-Compatible and 80L186-/80L188-Compatible, 16-Bit Embedded Microcontrollers
DISTINCTIVE CHARACTERISTICS
n E86TM family 80C186- and 80C188-compatible microcontrollers with enhanced bus interface -- Lower system cost with higher performance -- 3.3- V .3 -V ope ra tio n (A m1 86E MLV and AM188EMLV microcontrollers) n High performance -- 20-, 25-, 33-, and 40-MHz operating frequencies -- Supports zero-wait-state operation at 25 MHz with 110-ns static memory (Am186TMEMLV and Am188 TM EMLV microcontrollers) and 40 MHz with 70-ns static memory (Am186 TM EM and Am188TMEM microcontrollers) -- 1-Mbyte memory address space -- 64-Kbyte I/O space n New features provide faster access to memory and remove the requirement for a 2x clock input -- Nonmultiplexed address bus -- Phase-locked loop (PLL) allows processor to operate at the clock input frequency n New integrated peripherals provide increased functionality while reducing system cost -- Thirty-two programmable I/O (PIO) pins -- Asynchronous serial port allows full-duplex, 7-bit or 8-bit data transfers -- Synchronous serial interface allows half-duplex, bidirectional data transfer to and from ASICs -- Pseudo static RAM (PSRAM) controller includes auto refresh capability -- Reset configuration register Familiar 80C186/80L186 peripherals -- Two independent DMA channels -- Programmable interrupt controller with six external interrupts -- Three programmable 16-bit timers--timer 1 can be used as a watchdog interrupt timer -- Programmable memory and peripheral chip-select logic -- Programmable wait state generator -- Power-save clock divider Software-compatible with the 80C186/80C188 and 80L186 /80L188 microcontrollers Widely available native development tools, applications, and system software Available in the following packages: -- 100-pin, thin quad flat pack (TQFP) -- 100-pin, plastic quad flat pack (PQFP)
n
n n n
GENERAL DESCRIPTION
The Am186TMEM/EMLV and Am188TMEM/EMLV microcontrollers are the ideal upgrade for 80C186/188 and 80L186/188 microcontroller designs requiring 80C186/ 188 and 80L186/188 microcontroller compatibility, increased performance, serial communications, and a direct bus interface. The Am186EM/EMLV and AM188EM/EMLV microcontrollers increase the performance of existing 80C186/188 and 80L186/188 systems while decreasing their cost. The Am186EM/EMLV and AM188EM/EMLV microcontrollers are part of the AMD E86 family of embedded microcontrollers and microprocessors based on the x86 architecture. The E86 family includes the 16- and 32-bit microcontrollers and microprocessors described on page 8 The Am186EM/EMLV and AM188EM/EMLV microcontrollers integrate the functions of the CPU, nonmultiplexed address bus, timers, chip selects, interrupt controller, DMA controller, PSRAM controller, asynchronous serial port, synchronous serial interface, and programmable I/O (PIO) pins on one chip. Compared to the 80C186/188 and 80L186/188 microcontrollers, the Am186EM/EMLV and AM188EM/EMLV microcontrollers enable designers to reduce the size, power consumption, and cost of embedded systems, while increasing functionality and performance. The Am186EM/EMLV and AM188EM/EMLV microcontrollers have been designed to meet the most common requirements of embedded products developed for the office automation, mass storage, communications, and general embedded markets. Specific applications include disk drives, hand-held terminals and desktop terminals, fax machines, printers, photocopiers, feature phones, cellular phones, PBXs, multiplexers, modems, and industrial controls.
Publication# 19168 Rev: E Amendment/0 Issue Date: February 1997
This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice.
PRELIMINARY
Am186EM MICROCONTROLLER BLOCK DIAGRAM
INT2/INTA0 INT3/INTA1/IRQ CLKOUTA CLKOUTB INT4 INT1/SELECT INT0 NMI TMROUT0 TMRIN0 TMROUT1 DRQ0 DRQ1
TMRIN1
X2 X1
VCC GND
Clock and Power Management Unit
Interrupt Control Unit
Control Registers
Control Registers
Timer Control Unit 0 1 (WDT) Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers
DMA Unit 2 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
RES
PIO Unit
PIO31- PIO0*
Control Registers
ARDY SRDY S2-S0 DT/R DEN HOLD HLDA S6/ CLKDIV2 UZI
Refresh Control Unit
PSRAM Control Unit
Control Registers
Control Registers Asynchronous Serial Port Control Registers Synchronous Serial Interface
TXD RXD
Bus Interface Unit
Execution Unit
Chip-Select Unit
RD WHB A19-A0 AD15-AD0 WR BHE/ADEN ALE WLB LCS/ONCE0 MCS3/RFSH MCS2-MCS0
SCLK PCS6/A2 PCS5/A1 PCS3-PCS0
SDATA
SDEN0 SDEN1
UCS/ONCE1
Note: * All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared functions.
2
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
AM188EM MICROCONTROLLER BLOCK DIAGRAM
INT2/INTA0 INT3/INTA1/IRQ CLKOUTA CLKOUTB INT4 INT1/SELECT INT0 NMI TMROUT0 TMRIN0 TMROUT1 DRQ0 DRQ1
TMRIN1
X2 X1
VCC GND
Clock and Power Management Unit
Interrupt Control Unit
Control Registers
Control Registers
Timer Control Unit 0 1 (WDT) Max Count B Registers Max Count A Registers 16-Bit Count Registers Control Registers
DMA Unit 2 0 1 20-Bit Source Pointers 20-Bit Destination Pointers 16-Bit Count Registers Control Registers Control Registers
RES
PIO Unit
PIO31- PIO0*
Control Registers
ARDY SRDY S2-S0 DT/R DEN HOLD HLDA S6/ CLKDIV2 UZI
Refresh Control Unit
PSRAM Control Unit
Control Registers
Control Registers Asynchronous Serial Port Control Registers Synchronous Serial Interface
TXD RXD
Bus Interface Unit
Execution Unit
Chip-Select Unit
RD A19-A0 AO15-AO8 AD7-AD0 WR RFSH2/ADEN ALE WB LCS/ONCE0 MCS3/RFSH MCS2-MCS0
SCLK PCS6/A2 PCS5/A1 PCS3-PCS0
SDATA
SDEN0 SDEN1
UCS/ONCE1
Note: * All PIO signals are shared with other physical pins. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared functions.
Am186/188EM and Am186/188EMLV Microcontrollers
3
PRELIMINARY
ORDERING INFORMATION Standard Products
AMD standard products are available in several packages and operating ranges. The order numbers (valid combinations) are formed by a combination of the elements below.
Am186EM -40 V C \W LEAD FORMING \W=Trimmed and Formed TEMPERATURE RANGE C=EM Commercial (TC =0C to +100C) C=EMLV Commercial (TA =0C to +70C) I=EM Industrial (TA =-40C to +85C) (5-V only) Where: TC = case temperature TA = ambient temperature PACKAGE TYPE V=100-pin, thin quad flat pack (TQFP) K=100-pin, plastic quad flat pack (PQFP) SPEED OPTION -20 = 20 MHz -25 = 25 MHz -33 = 33 MHz -40 = 40 MHz DEVICE NUMBER/DESCRIPTION Am186EM High-Performance, 80C186-Compatible, 16-Bit Embedded Microcontroller AM188EM High-Performance, 80C188-Compatible, 16-Bit Embedded Microcontroller Am186EMLV High-Performance, 80L186-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller AM188EMLV High-Performance, 80L188-Compatible, Low-Voltage, 16-Bit Embedded Microcontroller Valid Combinations Valid combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations.
Valid Combinations Am186EM-20 Am186EM-25 Am186EM-33 Am186EM-40 AM188EM-20 AM188EM-25 AM188EM-33 AM188EM-40 Am186EM-20 Am186EM-25 AM188EM-20 AM188EM-25 Am186EMLV-20 Am186EMLV-25 AM188EMLV-20 AM188EMLV-25 VC\W or KC\W
VC\W or KC\W
KI\W KI\W VC\W or KC\W VC\W or KC\W
Notes: 1. The Am186EM and AM188EM industrial microcontrollers, as well as the Am186EMLV and AM188EMLV commercial microcontrollers, are available in 20- and 25-MHz operating frequencies only. 2. The Am186EM and AM188EM industrial microcontrollers are not offered in a low-voltage operating range. 3. The Am186EM, AM188EM, Am186EMLV, and AM188EMLV microcontrollers are all functionally the same except for their DC characteristics and available frequencies.
4
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
TABLE OF CONTENTS
Distinctive Characteristics ............................................................................................................ 1 General Description ..................................................................................................................... 1 Am186EM Microcontroller Block Diagram .................................................................................... 2 AM188EM Microcontroller Block Diagram .................................................................................... 3 Ordering Information .................................................................................................................... 4 Related AMD Products ................................................................................................................ 8 Key Features and Benefits ........................................................................................................ 10 TQFP Connection Diagrams and Pinouts .................................................................................. 11 PQFP Connection Diagrams and Pinouts ................................................................................. 17 Logic Symbol--Am186EM Microcontroller ................................................................................ 23 Logic Symbol--AM188EM Microcontroller ................................................................................ 24 Pin Descriptions Pins that Are Used by Emulators ................................................................................... 25 A19-A0 ........................................................................................................................... 25 AD7-AD0 ....................................................................................................................... 25 AD15-AD8 (Am186EM Microcontroller) ......................................................................... 25 AO15-AO8 (AM188EM Microcontroller) ........................................................................ 25 ALE ................................................................................................................................ 25 ARDY ............................................................................................................................. 25 BHE/ADEN (Am186EM Microcontroller Only) ............................................................... 26 CLKOUTA ...................................................................................................................... 26 CLKOUTB ...................................................................................................................... 26 DEN/PIO5 ...................................................................................................................... 26 DRQ1-DRQ0 .................................................................................................................. 26 DT/R/PIO4 ..................................................................................................................... 26 GND ............................................................................................................................... 27 HLDA ............................................................................................................................. 27 HOLD ............................................................................................................................. 27 INT0 ............................................................................................................................... 27 INT1/SELECT ................................................................................................................ 27 INT2/INTA0/PIO31 ......................................................................................................... 27 INT3/INTA1/IRQ ............................................................................................................. 27 INT4/PIO30 .................................................................................................................... 28 LCS/ONCE0 ................................................................................................................... 28 MCS3/RFSH/PIO25 ....................................................................................................... 28 MCS2-MCS0 .................................................................................................................. 28 NMI ................................................................................................................................ 28 PCS3-PCS0 ................................................................................................................... 29 PCS5/A1/PIO3 ............................................................................................................... 29 PCS6/A2/PIO2 ............................................................................................................... 29 PIO31-PIO0 (Shared) .................................................................................................... 29 RD .................................................................................................................................. 31 RES ................................................................................................................................ 31 RFSH2/ADEN (AM188EM Microcontroller Only) ........................................................... 31 RXD/PIO28 .................................................................................................................... 31 S2-S0 ............................................................................................................................ 31 S6/CLKDIV2/PIO29 ....................................................................................................... 31 SCLK/PIO20 .................................................................................................................. 32 SDATA/PIO21 ................................................................................................................ 32 SDEN1/PIO23, SDEN0/PIO22 ....................................................................................... 32 SRDY/PIO6 .................................................................................................................... 32 TMRIN0/PIO11 .............................................................................................................. 32
Am186/188EM and Am186/188EMLV Microcontrollers
5
PRELIMINARY
TMRIN1/PIO0 ................................................................................................................ 32 TMROUT0/PIO10 .......................................................................................................... 32 TMROUT1/PIO1 ............................................................................................................ 32 TXD/PIO27 ..................................................................................................................... 32 UCS/ONCE1 .................................................................................................................. 32 UZI/PIO26 ...................................................................................................................... 33 VCC ................................................................................................................................. 33 WHB (Am186EM Microcontroller Only) ......................................................................... 33 WLB (Am186EM Microcontroller Only) ........................................................................... 33 WB (AM188EM Microcontroller Only) ............................................................................ 33 WR ................................................................................................................................. 33 X1 ................................................................................................................................... 33 X2 ................................................................................................................................... 33 Functional Description ............................................................................................................... 34 Bus Operation ............................................................................................................................ 35 Bus Interface Unit ....................................................................................................................... 37 Peripheral Control Block (PCB) ................................................................................................. 38 Clock and Power Management .................................................................................................. 41 Chip-Select Unit.......................................................................................................................... 43 Refresh Control Unit .................................................................................................................. 45 Interrupt Control Unit ................................................................................................................. 45 Timer Control Unit ...................................................................................................................... 46 Direct Memory Access (DMA) ................................................................................................... 46 Asynchronous Serial Port .......................................................................................................... 48 Synchronous Serial Interface ..................................................................................................... 48 Programmable I/O (PIO) Pins .................................................................................................... 50 Absolute Maximum Ratings ....................................................................................................... 51 Operating Ranges ...................................................................................................................... 51 DC Characteristics Over Commercial Operating Range ........................................................... 51 Commercial Switching Characteristics and Waveforms ............................................................ 60
6
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
LIST OF FIGURES
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Example System Design ........................................................................................ 10 Two-Component Address ...................................................................................... 34 Am186EM Microcontroller Address Bus--Normal Read and Write Operation ...... 35 Am186EM Microcontroller--Read and Write with Address Bus Disable In Effect ..................................................................................................... 36 AM188EM Microcontroller Address Bus--Normal Read and Write Operation ...... 36 AM188EM Microcontroller--Read and Write with Address Bus Disable In Effect ..................................................................................................... 37 Peripheral Control Block Register Map .................................................................. 39 Am186EM and AM188EM Microcontrollers Oscillator Configurations ................... 41 Clock Organization ................................................................................................ 42 DMA Unit Block Diagram ....................................................................................... 47 Synchronous Serial Interface Multiple Write .......................................................... 49 Synchronous Serial Interface Multiple Read .......................................................... 49 Typical ICC Versus Frequency for the Am186EMLV and AM188EMLV ................ 53 Typical ICC Versus Frequency for the Am186EM and AM188EM ......................... 53 Thermal Resistance(C/Watt) ................................................................................ 54 Thermal Characteristics Equations ........................................................................ 54 Typical Ambient Temperatures for PQFP with 2-Layer Board ............................... 56 Typical Ambient Temperatures for TQFP with 2-Layer Board ............................... 57 Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board ............. 58 Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board .............. 59
LIST OF TABLES
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Data Byte Encoding ............................................................................................... 26 Numeric PIO Pin Assignments .............................................................................. 30 Alphabetic PIO Pin Assignments ........................................................................... 30 Bus Cycle Encoding ............................................................................................... 31 Segment Register Selection Rules ........................................................................ 34 Am186EM Microcontroller Maximum DMA Transfer Rates ................................... 46 Typical Power Consumption Calculation for the Am186EMLV and AM188EMLV ............................................................................ 53 Thermal Characteristics (C/Watt) ......................................................................... 54 Typical Power Consumption Calculation ............................................................... 55 Junction Temperature Calculation ......................................................................... 55 Typical Ambient Temperatures for PQFP with 2-Layer Board ............................... 56 Typical Ambient Temperatures for TQFP with 2-Layer Board ............................... 57 Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board ............. 58 Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board .............. 59
Am186/188EM and Am186/188EMLV Microcontrollers
7
PRELIMINARY
Microprocessors AT Peripheral Microcontrollers 186 Peripheral Microcontrollers Am386SX/DX Microprocessors ElanSC310 Microcontroller ElanSC300 Microcontroller Am186EM and AM188EM Microcontrollers Am186EMLV & AM188EMLV Microcontrollers Am486DX Microprocessor AMD-K5TM Microprocessor
K86TM Future Am486 Future 32-bit Future Am186ER and Am188ER Microcontrollers Am186ES and Am188ES Microcontrollers Am186ESLV & Am188ESLV Microcontrollers
ElanSC400 Microcontroller
Am186 and Am188 Future
80C186 and 80C188 Microcontrollers 80L186 and 80L188 Microcontrollers
Time The E86 Family of Embedded Microprocessors and Microcontrollers
RELATED AMD PRODUCTS E86TM Family Devices
Device 80C186 80C188 80L186 80L188 Am186EM AM188EM Am186EMLV AM188EMLV Description 16-bit microcontroller 16-bit microcontroller with 8-bit external data bus Low-voltage, 16-bit microcontroller Low-voltage, 16-bit microcontroller with 8-bit external data bus High-performance, 80C186-compatible, 16-bit embedded microcontroller High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ES High-performance, 80C186-compatible, 16-bit embedded microcontroller Am188ES High-performance, 80C188-compatible, 16-bit embedded microcontroller with 8-bit external data bus Am186ESLV High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller Am188ESLV High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus Am186ER High-performance, 80C186-compatible, low-voltage, 16-bit embedded microcontroller with 32 Kbyte of internal RAM Am188ER High-performance, 80C188-compatible, low-voltage, 16-bit embedded microcontroller with 8-bit external data bus and 32 Kbyte of internal RAM ElanTMSC300 High-performance, highly integrated, low-voltage, 32-bit embedded microcontroller ElanSC310 High-performance, single-chip, 32-bit embedded PC/AT microcontroller ElanSC400 Single-chip, low-power, PC/AT-compatible microcontroller Am386(R)DX Am386SX Am486(R)DX 8 High-performance, 32-bit embedded microprocessor with 32-bit external data bus High-performance, 32-bit embedded microprocessor with 16-bit external data bus High-performance, 32-bit embedded microprocessor with 32-bit external data bus Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Related Documents
The following documents provide additional information regarding the Am186EM and AM188EM microcontrollers. n The Am186EM and AM188EM Microcontrollers User's Manual, order# 19713 n The Am186 and Am188 Family Instruction Set Manual, order# 21267 n The FusionE86SM Catalog, order# 19255
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Third-Party Development Support Products
The FusionE86 Program of Partnerships for Application Solutions provides the customer with an array of products designed to meet critical time-to-market needs. Products and solutions available from the AMD FusionE86 partners include emulators, hardware and software debuggers, board-level products, and software development tools, among others. In addition, mature development tools and applications for the x86 platform are widely available in the general marketplace.
Documentation and Literature Free E86 family information such as data books, user's man ual s , data sh eets , ap pl ic ati on n otes , th e FusionE86 Partner Solutions Catalog, and other literature is available with a simple phone call. Internationally, contact your local AMD sales office for complete E86 family literature. Literature Ordering 800-222-9323 512-602-5651 800-222-9323 Toll-free for U.S. and Canada Direct dial worldwide AMD Facts-On-DemandTM fax information service, toll-free for U.S. and Canada
Customer Service
The AMD customer service network includes U.S. offices, international offices, and a customer training center. Expert technical assistance is available from the AMD worldwide staff of field application engineers and factory support staff who can answer E86 family hardware and software development questions. Hotline and World Wide Web Support For answers to technical questions, AMD provides a toll-free number for direct access to our corporate applications hotline. Also available is the AMD World Wide Web home page and FTP site, which provides the latest E86 family product information, including technical information and data on upcoming product releases.
Am186/188EM and Am186/188EMLV Microcontrollers
9
PRELIMINARY
KEY FEATURES AND BENEFITS
The Am186EM and AM188EM microcontrollers extend the AMD family of microcontrollers based on the industry-standard x86 architecture. The Am186EM and AM188EM microcontrollers are higher-performance, more integrated versions of the 80C186/188 microprocessors, offering a migration path that was previously unava ilabl e. Upgr adi ng to the Am 186EM and AM188EM microcontrollers is an attractive solution for several reasons: n Minimized total system cost--New peripherals and on-chip system interface logic on the Am186EM and AM188EM microcontrollers reduce the cost of existing 80C186/188 designs. n X86 software compatibility--80C186/188-compatible and upward-compatible with the other members of the AMD E86 family. n Enhanced performance--The Am186EM and AM188EM microcontrollers increase the performance of 80C186/188 systems, and the demultiplexed address bus offers faster, unbuffered access to memory. n Enhanced functionality--The new and enhanced on-chip peripherals of the Am186EM and AM188EM microcontrollers include an asynchronous serial port, 32 PIOs, a watchdog timer, an additional interrupt pin, a synchronous serial interface, a PSRAM controller, a 16-bit reset configuration register, and enhanced chip-select functionality.
dress latch enable (ALE) signal is no longer needed. Individual byte-write-enable signals are provided to eliminate the need for external high/low byte-write-enable circuitry. The maximum bank size that is programmable for the memory chip-select signals has been increased to facilitate the use of high-density memory devices. The improved memory timing specifications for the Am186EM and AM188EM microcontrollers allow no wait-state operation with 70-ns memory access times at a 40-MHz CPU clock speed. This reduces overall system cost significantly by allowing the use of a more commonly available memory speed and technology. Direct Memory Interface Example Figure 1 illustrates the Am186EM microcontroller direct memory interface. The processor A19-A0 bus connects to the memory address inputs, the AD bus connects to the data inputs and outputs, and the chip selects connect to the memory chip-select inputs. The RD output connects to the SRAM Output Enable (OE) pin for read operations. Write operations use the byte write enables connected to the SRAM Write Enable (WE) pins. The example design uses 2-Mbit memory technology (256 Kbytes) to fully populate the available address space. Two flash PROM devices provide 512 Kbytes of nonvolatile program storage and two static RAM devices provide 512 Kbytes of data storage area. Figure 1 also shows an implementation of an RS-232 console or modem communications port. The RS-232to-CMOS voltage-level converter is required for the electrical interface with the external device.
Application Considerations
The integration enhancements of the Am186EM and AM188EM microcontrollers provide a high-performance, low-system-cost solution for 16-bit embedded microcontroller designs. The nonmultiplexed address bus eliminates the need for system-support logic to interface memory devices, while the multiplexed address/data bus maintains the value of previously engineered, customer-specific peripherals and circuits within the upgraded design. Figure 1 illustrates an example system design that uses the integrated peripheral set to achieve high performance with reduced system cost. Clock Generation The integrated clock generation circuitry of the Am186EM and AM188EM microcontrollers allows the use of a times-one crystal frequency. The design in Figure 1 achieves 40-MHz CPU operation while using a 40-MHz crystal. Memory Interface The integrated memory controller logic of the Am186EM and AM188EM microcontrollers provides a direct address bus interface to memory devices. The use of an external address latch controlled by the ad-
Am186EM Microcontroller
X2 X1 40-MHz Crystal WHB WLB A19-A0 AD15-AD0 RD UCS
Flash PROM
WE WE Address Data OE CS
Static RAM Serial Port
RS-232 Level Converter TXD RXD Data OE LCS CS WE WE Address
Figure 1.
Example System Design
10
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
TQFP CONNECTION DIAGRAMS AND PINOUTS Am186EM Microcontroller Top Side View--100-Pin Thin Quad Flat Pack (TQFP)
MCS2 VCC
100
99 98 97
96 95
94 93
92
91 90 89
88
87 86 85
84
GND PCS 2 PCS 3 VCC
83 82 81
80
79 78 77
AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 VCC AD14 AD7 AD15 S6/CLKDIV2 UZI TXD RXD SDATA SDEN1 SDEN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 42 43 44 45 46 47 48 49 28 29 32 33 34 35 36 37 38 39 30 31 40 41 50
76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
INT3/INTA1/IRQ
INT0 INT1/ SELECT INT2/INTA0
UCS / ONCE1
PCS 5/A1 PCS 6/A2 LCS / ONCE 0
MCS3/ RFSH
DRQ1 TMRIN0 TMROUT0
TMROUT1 TMRIN1
DRQ0
PCS 0
PCS 1
RES GND
INT4 MCS1 MCS0 DEN DT/R NMI SRDY HOLD HLDA WLB WHB GND A0 A1 VCC A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
Am186EM Microcontroller
SCLK
BHE/ADEN WR RD ALE ARDY
CLKOUTB GND A19 A18
GND X1 X2
VCC CLKOUTA
VCC A17
A16 A15
A14 A13
Note: Pin 1 is marked for orientation.
Am186/188EM and Am186/188EMLV Microcontrollers
A12
S2 S1
S0
11
PRELIMINARY
TQFP PIN ASSIGNMENTS--Am186EM Microcontroller (Sorted by Pin Number)
Pin No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 VCC AD14 AD7 AD15 S6/CKLDIV2/PIO29 UZI/PIO26 TXD RXD SDATA/PIO21 SDEN1/PIO23 SDEN0/PIO22 Pin No. Name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SCLK/PIO20 BHE/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 A13 A12 Pin No. Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND WHB WLB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/PIO5 MCS0/PIO14 MCS1/PIO15 INT4 Pin No. Name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 INT3/INTA1/IRQ INT2/INTA0 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/PIO19 PCS2/PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2 MCS3/RFSH GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 DRQ1/PIO13 DRQ0/PIO12
12
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
TQFP PIN ASSIGNMENTS--Am186EM Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 1 3 5 7 9 Pin Name AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE/ADEN CLKOUTA CLKOUTB DEN/PIO5 DRQ0/PIO12 DRQ1/PIO13 DT/R/PIO4 GND GND GND GND GND No. 11 14 17 2 4 6 8 10 13 16 18 30 31 27 39 40 72 100 99 71 12 35 41 64 87 Pin Name GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0 INT3/INTA1/IRQ INT4 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2 MCS3/RFSH NMI PCS0/PIO16 PCS1/PIO17 PCS2/PIO18 PCS3/PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RXD S0 S1 No. 93 67 68 79 78 77 76 75 81 73 74 91 92 70 89 88 86 85 83 82 29 94 22 34 33 Pin Name S2 S6/CLKDIV2/PIO29 SCLK/PIO20 SDATA/PIO21 SDEN0/PIO22 SDEN1/PIO23 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/PIO10 TMROUT1/PIO1 TXD UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WHB WLB WR X1 X2 No. 32 19 26 23 25 24 69 98 95 97 96 21 80 20 15 38 44 61 84 90 65 66 28 36 37
Am186/188EM and Am186/188EMLV Microcontrollers
13
PRELIMINARY
CONNECTION DIAGRAM AM188EM Microcontroller Top Side View--100-Pin Thin Quad Flat Pack (TQFP)
INT3/INTA1/IRQ 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 42 43 44 45 46 47 48 49 27 28 29 32 33 34 35 36 37 38 39 30 31 40 41 50 INT0 INT1/ SELECT INT2/INTA0 79 78 77 UCS / ONCE1 80 PCS 5/A1 PCS 6/A2 LCS / ONCE 0 83 82 81 MCS3/ RFSH
DRQ1 TMRIN0 TMROUT0
TMROUT1 TMRIN1
MCS2 VCC
DRQ0
100
99 98 97
96 95
94 93
92
91 90 89
88
87 86 85
AD0 AO8 AD1 AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15 S6/CLKDIV2 UZI TXD RXD SDATA SDEN1 SDEN0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
84
GND PCS 2 PCS 3 VCC
PCS 0
PCS 1
RES GND
INT4 MCS1 MCS0 DEN DT/R NMI SRDY HOLD HLDA WB GND GND A0 A1 VCC A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
AM188EM Microcontroller
SCLK
RFSH2/ADEN WR RD ALE ARDY
CLKOUTB GND A19 A18
GND X1 X2
VCC CLKOUTA
VCC A17
A16 A15
A14 A13
Note: Pin 1 is marked for orientation.
14
Am186/188EM and Am186/188EMLV Microcontrollers
A12
S2 S1
S0
PRELIMINARY
TQFP PIN ASSIGNMENTS--AM188EM Microcontroller (Sorted by Pin Number)
Pin No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 AD0 AO8 AD1 AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15 S6/CLKDIV2/PIO29 UZI/PIO26 TXD/PIO27 RXD/PIO28 SDATA/PIO21 SDEN1/PIO23 SDEN0/PIO22 Pin No. Name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 SCLK/PIO20 RFSH2/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 A13 A12 Pin No. Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND GND WB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/PIO5 MCS0/PIO14 MCS1/PIO15 INT4/PIO30 Pin No. Name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 INT3/INTA1/IRQ INT2/INTA0/PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/PIO19 PCS2/PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 DRQ1/PIO13 DRQ0/PIO12
Am186/188EM and Am186/188EMLV Microcontrollers
15
PRELIMINARY
TQFP PIN ASSIGNMENTS--AM188EM Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 63 62 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 43 42 1 3 5 7 9 Pin Name AD5 AD6 AD7 ALE AO8 AO9 AO10 AO11 AO12 AO13 AO14 AO15 ARDY CLKOUTA CLKOUTB DEN/PIO5 DRQ0/PIO12 DRQ1/PIO13 DT/R/PIO4 GND GND GND GND GND GND No. 11 14 17 30 2 4 6 8 10 13 16 18 31 39 40 72 100 99 71 12 35 41 64 65 87 Pin Name GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/PIO18 PCS3/PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RFSH2/ADEN RXD/PIO28 S0 No. 93 67 68 79 78 77 76 75 81 73 74 91 92 70 89 88 86 85 83 82 29 94 27 22 34 Pin Name S1 S2 S6/CLKDIV2/PIO29 SCLK/PIO20 SDATA/PIO21 SDEN0/PIO22 SDEN1/PIO23 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/PIO10 TMROUT1/PIO1 TXD/PIO27 UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WB WR X1 X2 No. 33 32 19 26 23 25 24 69 98 95 97 96 21 80 20 15 38 44 61 84 90 66 28 36 37
16
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PQFP CONNECTION DIAGRAMS AND PINOUTS Am186EM Microcontroller Top Side View--100-Pin Plastic Quad Flat Pack (PQFP)
S6/CLKDIV 2
SDATA RXD TXD
AD12 AD4
AD7 AD14
AD13
AD15
100
99
98
97
UZI
96
95
94
93
92
91
90
89
88
87
86
85
84
AD11 AD3
GND AD5
AD6
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SDEN1 SDEN0 SCLK BHE/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AD10 AD2 AD9
VCC
AD1 AD8 AD0 DRQ0 DRQ1 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH MCS2 VCC PCS0 PCS1 GND PCS2 PCS3 VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0 INT3/INTA1/IRQ INT4 MCS1
Am186EM Microcontroller
HOLD
SRDY
HLDA
NMI DT/R
Note: Pin 1 is marked for orientation.
Am186/188EM and Am186/188EMLV Microcontrollers
DEN MCS0
VCC A1
WHB WLB
A0 GND
A8 A7
A6
A5
A4
A3 A2
17
PRELIMINARY
PQFP PIN ASSIGNMENTS--Am186EM Microcontroller (Sorted by Pin Number)
Pin No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDEN1/PIO23 SDEN0/PIO22 SCLK/PIO20 BHE/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 Pin No. Name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND WHB WLB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/PIO5 MCS0/PIO14 Pin No. Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 MCS1/PIO15 INT4/PIO30 INT3/INTA1/IRQ INT2/INTA0/PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/PIO19 PCS2/PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 Pin No. Name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DRQ1/PIO13 DRQ0/PIO12 AD0 AD8 AD1 AD9 AD2 AD10 AD3 AD11 AD4 AD12 AD5 GND AD13 AD6 VCC AD14 AD7 AD15 S6/CLKDIV2/PIO29 UZI/PIO26 TXD/PIO27 RXD/PIO28 SDATA/PIO21
18
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PQFP PIN ASSIGNMENTS--Am186EM Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 78 80 82 84 86 Pin Name AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 ALE ARDY BHE/ADEN CLKOUTA CLKOUTB DEN/PIO5 DRQ0/PIO12 DRQ1/PIO13 DT/R/PIO4 GND GND GND GND GND No. 88 91 94 79 81 83 85 87 90 93 95 7 8 4 16 17 49 77 76 48 12 18 41 64 70 Pin Name GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/PIO18 PCS3/PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RXD/PIO28 S0 S1 No. 89 44 45 56 55 54 53 52 58 50 51 68 69 47 66 65 63 62 60 59 6 71 99 11 10 Pin Name S2 S6/CLKDIV2/PIO29 SCLK/PIO20 SDATA/PIO21 SDEN0/PIO22 SDEN1/PIO23 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/PIO10 TMROUT1/PIO1 TXD/PIO27 UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WHB WLB WR X1 X2 No. 9 96 3 100 2 1 46 75 72 74 73 98 57 97 15 21 38 61 67 92 42 43 5 13 14
Am186/188EM and Am186/188EMLV Microcontrollers
19
PRELIMINARY
CONNECTION DIAGRAM AM188EM Microcontroller Top Side View--100-Pin Plastic Quad Flat Pack (PQFP)
S6/CLKDIV 2
SDATA RXD TXD
AD12 AD4
AD7 AD14
AD13
AD15
100
99
98
97
UZI
96
95
94
93
92
91
90
89
88
87
86
85
84
AD11 AD3
GND AD5
AD6
83
82
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SDEN1 SDEN0 SCLK RFSH2/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19 A18 VCC A17 A16 A15 A14 A13 A12 A11 A10 A9
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
AD10 AD2 AD9
VCC
AD1 AD8 AD0 DRQ0 DRQ1 TMRIN0 TMROUT0 TMROUT1 TMRIN1 RES GND MCS3/RFSH MCS2 VCC PCS0 PCS1 GND PCS2 PCS3 VCC PCS5/A1 PCS6/A2 LCS/ONCE0 UCS/ONCE1 INT0 INT1/SELECT INT2/INTA0 INT3/INTA1/IRQ INT4 MCS1
AM188EM Microcontroller
HOLD
SRDY
HLDA
NMI DT/R
Note: Pin 1 is marked for orientation.
20
Am186/188EM and Am186/188EMLV Microcontrollers
DEN MCS0
VCC A1
A0 GND
GND WB
A8 A7
A6
A5
A4
A3 A2
PRELIMINARY
PQFP PIN ASSIGNMENTS--AM188EM Microcontroller (Sorted by Pin Number)
Pin No. Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 SDEN1/PIO23 SDEN0/PIO22 SCLK/PIO20 RFSH2/ADEN WR RD ALE ARDY S2 S1 S0 GND X1 X2 VCC CLKOUTA CLKOUTB GND A19/PIO9 A18/PIO8 VCC A17/PIO7 A16 A15 A14 Pin No. Name 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 VCC A1 A0 GND GND WB HLDA HOLD SRDY/PIO6 NMI DT/R/PIO4 DEN/PIO5 MCS0/PIO14 Pin No. Name 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 MCS1/PIO15 INT4/PIO30 INT3/INTA1/IRQ INT2/INTA0/PIO31 INT1/SELECT INT0 UCS/ONCE1 LCS/ONCE0 PCS6/A2/PIO2 PCS5/A1/PIO3 VCC PCS3/PIO19 PCS2/PIO18 GND PCS1/PIO17 PCS0/PIO16 VCC MCS2/PIO24 MCS3/RFSH/PIO25 GND RES TMRIN1/PIO0 TMROUT1/PIO1 TMROUT0/PIO10 TMRIN0/PIO11 Pin No. Name 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 DRQ1/PIO13 DRQ0/PIO12 AD0 AO8 AD1 AO9 AD2 AO10 AD3 AO11 AD4 AO12 AD5 GND AO13 AD6 VCC AO14 AD7 AO15 S6/CLKDIV2/PIO29 UZI/PIO26 TXD/PIO27 RXD/PIO28 SDATA/PIO21
Am186/188EM and Am186/188EMLV Microcontrollers
21
PRELIMINARY
PQFP PIN ASSIGNMENTS--AM188EM Microcontroller (Sorted by Pin Name)
Pin Name A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17/PIO7 A18/PIO8 A19/PIO9 AD0 AD1 AD2 AD3 AD4 No. 40 39 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 20 19 78 80 82 84 86 Pin Name AD5 AD6 AD7 ALE AO8 AO9 AO10 AO11 AO12 AO13 AO14 AO15 ARDY CLKOUTA CLKOUTB DEN/PIO5 DRQ0/PIO12 DRQ1/PIO13 DT/R/PIO4 GND GND GND GND GND GND No. 88 91 94 7 79 81 83 85 87 90 93 95 8 16 17 49 77 76 48 12 18 41 42 64 70 Pin Name GND HLDA HOLD INT0 INT1/SELECT INT2/INTA0/PIO31 INT3/INTA1/IRQ INT4/PIO30 LCS/ONCE0 MCS0/PIO14 MCS1/PIO15 MCS2/PIO24 MCS3/RFSH/PIO25 NMI PCS0/PIO16 PCS1/PIO17 PCS2/PIO18 PCS3/PIO19 PCS5/A1/PIO3 PCS6/A2/PIO2 RD RES RFSH2/ADEN RXD/PIO28 S0 No. 89 44 45 56 55 54 53 52 58 50 51 68 69 47 66 65 63 62 60 59 6 71 4 99 11 Pin Name S1 S2 S6/CLKDIV2/PIO29 SCLK/PIO20 SDATA/PIO21 SDEN0/PIO22 SDEN1/PIO23 SRDY/PIO6 TMRIN0/PIO11 TMRIN1/PIO0 TMROUT0/PIO10 TMROUT1/PIO1 TXD/PIO27 UCS/ONCE1 UZI/PIO26 VCC VCC VCC VCC VCC VCC WB WR X1 X2 No. 10 9 96 3 100 2 1 46 75 72 74 73 98 57 97 15 21 38 61 67 92 43 5 13 14
22
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
LOGIC SYMBOL--Am186EM MICROCONTROLLER
X1 X2 Clocks CLKOUTA CLKOUTB INT3/INTA1/IRQ INT2/INTA0 INT1/SELECT INT0 * Address and Address/Data Buses * * 20 16 A19-A0 AD15-AD0 S6/CLKDIV2 UZI PCS6/A2 PCS5/A1 ALE 3 S2-S0 HOLD HLDA RD WR Bus Control * * DT/R DEN ARDY * SRDY BHE/ADEN WHB 2 WLB DRQ1-DRQ0 * DMA Control PCS3-PCS0 LCS/ONCE0 MCS3/RFSH MCS2-MCS0 UCS/ONCE1 3 * * 4 * * * Memory and Peripheral Control NMI * Reset Control and Interrupt Service RES INT4 *
* Timer Control * * *
TMRIN0 TXD TMROUT0 RXD TMRIN1 TMROUT1 SDEN1-SDEN0 PIO32-PIO0 SCLK SDATA 2 * * * Synchronous Serial Port Control * * Asynchronous Serial Port Control
Programmable I/O Control
32 shared **
Notes: * These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared function. ** All PIO signals are shared with other physical pins.
Am186/188EM and Am186/188EMLV Microcontrollers
23
PRELIMINARY
LOGIC SYMBOL--AM188EM MICROCONTROLLER
X1 X2 Clocks CLKOUTA CLKOUTB INT3/INTA1/IRQ INT2/INTA0 INT1/SELECT INT0 * Address and Address/Data Buses * * 20 8 8 A19-A0 AO15-AO8 AD7-AD0 S6/CLKDIV2 UZI PCS6/A2 PCS5/A1 PCS3-PCS0 ALE 3 S2-S0 HOLD HLDA RD Bus Control * * WR DT/R DEN ARDY * SRDY RFSH2/ADEN WB DRQ1-DRQ0 2 DMA Control LCS/ONCE0 MCS3/RFSH MCS2-MCS0 UCS/ONCE1 3 * * 4 * * * Memory and Peripheral Control NMI * Reset Control and Interrupt Service RES INT4 *
*
* Timer Control * * * 32 shared **
TMRIN0 TXD TMROUT0 RXD TMRIN1 TMROUT1 SDEN1-SDEN0 PIO31-PIO0 SCLK SDATA 2 * * * Synchronous Serial Port Control * * Asynchronous Serial Port Control
Programmable I/O Control
Notes: * These signals are the normal function of a pin that can be used as a PIO. See the pin descriptions beginning on page 25 and Table 2 on page 30 for information on shared function. ** All PIO signals are shared with other physical pins.
24
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PIN DESCRIPTIONS Pins That Are Used by Emulators
The following pins are used by emulators: A19-A0, AO15-AO8, AD7-AD0, ALE, BHE/ADEN (on the Am186EM), CLKOUTA, R F S H 2/A D E N (on the AM188EM), RD, S2-S0, S6/CLKDIV2, and UZI. Emulators require that S6/CLKDIV2 and UZI be configured in their normal functionality, that is as S6 and UZI. If BHE/ADEN (on the 186) or RFSH2/ADEN (on the 188) is held Low during the rising edge of RES, S6 and UZI are configured in their normal functionality.
During a power-on reset, the address and data bus pins (AD15-AD0 for the 186, AO15-AO8 and AD7- AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register.
AD15-AD8 (Am186EM Microcontroller) AO15-AO8 (AM188EM Microcontroller)
Address and Data Bus (input/output, three-state, synchronous, level-sensitive) Address-Only Bus (output, three-state, synchronous, level-sensitive) AD15-AD8--On the Am186EM microcontroller, these time-multiplexed pins supply memory or I/O addresses and data to the system. This bus can supply an address to the system during the first period of a bus cycle (t1). It supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WHB is negated, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state. During a power-on reset, the address and data bus pins (AD15-AD0 for the 186, AO15-AO8 and AD7- AD0 for the 188) can also be used to load system configuration information into the internal reset configuration register. AO15-AO8--On the AM188EM microcontroller, the address-only bus (AO15-AO8) contains valid highorder address bits from bus cycles t1-t4. These outputs are floated during a bus hold or reset. On the AM188EM microcontroller, AO15-AO8 combine with AD7-AD0 to form a complete multiplexed address bus while AD7-AD0 is the 8-bit data bus.
Pin Terminology
The following terms are used to describe the pins: Input--An input-only pin. Output--An output-only pin. Input/Output--A pin that can be either input or output. Synchronous--Synchronous inputs must meet setup and hold times in relation to CLKOUTA. Synchronous outputs are synchronous to CLKOUTA. Asynchronous--Inputs or outputs that are asynchronous to CLKOUTA.
A19-A0 (A19/PIO9, A18/PIO8, A17/PIO7)
Address Bus (output, three-state, synchronous) These pins supply nonmultiplexed memory or I/O addresses to the system one-half of a CLKOUTA period earlier than the multiplexed address and data bus (AD15-AD0 on the 186 or AO15-AO8 and AD7-AD0 on the 188). During a bus hold or reset condition, the address bus is in a high-impedance state.
AD7-AD0
Address and Data Bus (input/output, three-state, synchronous, level-sensitive) These time-multiplexed pins supply partial memory or I/O addresses, as well as data, to the system. This bus supplies the low-order 8 bits of an address to the system during the first period of a bus cycle (t1), and it supplies data to the system during the remaining periods of that cycle (t2, t3, and t4). The address phase of these pins can be disabled. See the ADEN description with the BHE/ADEN pin. When WLB is negated, these pins are three-stated during t2, t3, and t4. During a bus hold or reset condition, the address and data bus is in a high-impedance state.
ALE
Address Latch Enable (output, synchronous) This pin indicates to the system that an address appears on the address and data bus (AD15-AD0 for the 186 or AO15-AO8 and AD7-AD0 for the 188). The address is guaranteed valid on the trailing edge of ALE. This pin is three-stated during ONCE mode. This pin is not three-stated during a bus hold or reset.
ARDY
Asynchronous Ready (input, asynchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The ARDY pin accepts a rising edge that is asynchronous to CLKOUTA and is active High. The
Am186/188EM and Am186/188EMLV Microcontrollers
25
PRELIMINARY falling edge of ARDY must be synchronized to CLKOUTA. To always assert the ready condition to the microcontroller, tie ARDY High. If the system does not use ARDY, tie the pin Low to yield control to SRDY. If BHE/ADEN is held Low on power-on reset, the AD bus drives both addresses and data, regardless of the DA bit setting. This pin is sampled on the rising edge of RES. (S6 and UZI also assume their normal functionality in this instance. See Table 2 on page 30.)
BHE/ADEN (Am186EM Microcontroller Only)
Bus High Enable (three-state, output, synchronous) Address Enable (input, internal pullup) BHE--During a memory access, this pin and the leastsignificant address bit (AD0 or A0) indicate to the system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The BHE/ADEN and AD0 pins are encoded as shown in Table 1. BHE is asserted during t 1 and remains asserted through t3 and tW. BHE does not need to be latched. BHE floats during bus hold and reset. On the Am186EM and AM188EM microcontrollers, WLB and WHB implement the functionality of BHE and AD0 for high and low byte write enables.
Note: On the AM188EM microcontroller, AO15-AO8 are driven during the entire bus cycle, regardless of the setting of the DA bit in the UMCS and LMCS registers.
CLKOUTA
Clock Output A (output, synchronous) This pin supplies the internal clock to the system. Depending on the value of the power-save control register (PDCON), CLKOUTA operates at either the crystal input frequency (X1), the power-save frequency, or is three-stated. CLKOUTA remains active during reset and bus hold conditions.
CLKOUTB
Clock Output B (output, synchronous) This pin supplies an additional clock to the system. Depending upon the value of the power-save control register (PDCON), CLKOUTB operates at either the crystal input frequency (X1), the power-save frequency, or is three-stated. CLKOUTB remains active during reset and bus hold conditions.
Table 1. Data Byte Encoding
BHE 0 0 1 1 AD0 Type of Bus Cycle 0 1 0 1 Word Transfer High Byte Transfer (Bits 15-8) Low Byte Transfer (Bits 7-0) Refresh
DEN/PIO5
Data Enable (output, three-state, synchronous) This pin supplies an output enable to an external databus transceiver. DEN is asserted during memory, I/O, and interrupt acknowledge cycles. DEN is deasserted when DT/R changes state. DEN floats during a bus hold or reset condition.
BHE/ADEN also signals DRAM refresh cycles when using the multiplexed address and data (AD) bus. A refresh cycle is indicated when both BHE/ADEN and AD0 are High. During refresh cycles, the A bus and the AD bus are not guaranteed to provide the same address during the address phase of the AD bus cycle. For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles. PSRAM refreshes also provide an additional RFSH signal (see the MCS3/RFSH pin description on page 28). ADEN--If BHE/ADEN is held High or left floating during power-on reset, the address portion of the AD bus (AD15-AD0 for the 186 or AO15-AO8 and AD7-AD0 for the 188) is enabled or disabled during LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the memory address is accessed on the A19-A0 pins. There is a weak internal pullup resistor on BHE/ADEN so no external pullup is required. This mode of operation reduces power consumption.
DRQ1-DRQ0 (DRQ1/PIO13, DRQ0/PIO12)
DMA Requests (input, synchronous, level-sensitive) These pins indicate to the microcontroller that an external device is ready for DMA channel 1 or channel 0 to perform a transfer. DRQ1-DRQ0 are level-triggered and internally synchronized. The DRQ signals are not latched and must remain active until serviced.
DT/R/PIO4
Data Transmit or Receive (output, three-state, synchronous) This pin indicates which direction data should flow through an external data-bus transceiver. When DT/R is asserted High, the microcontroller transmits data. When this pin is deasserted Low, the microcontroller receives data. DT/R floats during a bus hold or reset condition.
26
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
GND
Ground The ground pins connect the system ground to the microcontroller.
INT1/SELECT
Maskable Interrupt Request 1 (input, asynchronous) Slave Select (input, asynchronous) INT1--This pin indicates to the microcontroller that an interrupt request has occurred. If INT1 is not masked, the microcontroller transfers program execution to the location specified by the INT1 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT1 until the request is acknowledged. SELECT--When the microcontroller interrupt control unit is operating as a slave to an external interrupt controller, this pin indicates to the microcontroller that an interrupt type appears on the address and data bus. The INT0 pin must indicate to the microcontroller that an interrupt has occurred before the SELECT pin indicates to the microcontroller that the interrupt type appears on the bus.
HLDA
Bus Hold Acknowledge (output, synchronous) This pin is asserted High to indicate to an external bus master that the microcontroller has released control of the local bus. When an external bus master requests control of the local bus (by asserting HOLD), the microcontroller completes the bus cycle in progress and then relinquishes control of the bus to the external bus master by asserting HLDA and floating DEN, RD, WR, S2- S0, AD15-AD0, S6, A19-A0, BHE, WHB, WLB, and DT/R, and then driving the chip selects UCS, LCS, MCS3-MCS0, PCS6-PCS5, and PCS3-PCS0 High. When the external bus master has finished using the local bus, it indicates this to the microcontroller by deasserting HOLD. The microcontroller responds by deasserting HLDA. If the microcontroller requires access to the bus (i.e. for refresh), it will deassert HLDA before the external bus master deasserts HOLD. The external bus master must be able to deassert HOLD and allow the microcontroller access to the bus. See the timing diagrams for bus hold on page 92.
INT2/INTA0/PIO31
Maskable Interrupt Request 2 (input, asynchronous) Interrupt Acknowledge 0 (output, synchronous) INT2--This pin indicates to the microcontroller that an interrupt request has occurred. If the INT2 pin is not masked, the microcontroller transfers program execution to the location specified by the INT2 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT2 until the request is acknowledged. INT2 becomes INTA0 when INT0 is configured in cascade mode. INTA0--When the microcontroller interrupt control unit is operating in cascade mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT0. The peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type.
HOLD
Bus Hold Request (input, synchronous, level-sensitive) This pin indicates to the microcontroller that an external bus master needs control of the local bus. The Am186EM and AM188EM microcontrollers' HOLD latency time is a function of the activity occurring in the processor when the HOLD request is received. A DRAM request will delay a HOLD request when both requests are made at the same time. In addition, if locked transfers are performed, the HOLD latency time is increased by the length of the locked transfer. For more information, see the HLDA pin description.
INT0
Maskable Interrupt Request 0 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT0 pin is not masked, the microcontroller transfers program execution to the location specified by the INT0 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT0 until the request is acknowledged.
INT3/INTA1/IRQ
Maskable Interrupt Request 3 (input, asynchronous) Interrupt Acknowledge 1 (output, synchronous) Slave Interrupt Request (output, synchronous) INT3--This pin indicates to the microcontroller that an interrupt request has occurred. If the INT3 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT3 vector in the microcontroller interrupt vector table.
Am186/188EM and Am186/188EMLV Microcontrollers
27
PRELIMINARY Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT3 until the request is acknowledged. INT3 becomes INTA1 when INT1 is configured in cascade mode. INTA1--When the microcontroller interrupt control unit is operating in cascade mode or special fully-nested mode, this pin indicates to the system that the microcontroller needs an interrupt type to process the interrupt request on INT1. In both modes, the peripheral issuing the interrupt request must provide the microcontroller with the corresponding interrupt type. IRQ--When the microcontroller interrupt control unit is operating as a slave to an external master interrupt controller, this pin lets the microcontroller issue an interrupt request to the external master interrupt controller.
MCS3/RFSH/PIO25
Midrange Memory Chip Select 3 (output, synchronous, internal pullup) Automatic Refresh (output, synchronous) MCS3--This pin indicates to the system that a memory access is in progress to the fourth region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS3 is held High during a bus hold condition. In addition, this pin has a weak internal pullup resistor that is active during reset. RFSH--This pin provides a signal timed for auto refresh to PSRAM devices. It is only enabled to function as a refresh pulse when the PSRAM mode bit is set in the LMCS Register. An active Low pulse is generated for 1.5 clock cycles with an adequate deassertion period to ensure that overall auto refresh cycle time is met. This pin is not three-stated during a bus hold condition.
INT4/PIO30
Maskable Interrupt Request 4 (input, asynchronous) This pin indicates to the microcontroller that an interrupt request has occurred. If the INT4 pin is not masked, the microcontroller then transfers program execution to the location specified by the INT4 vector in the microcontroller interrupt vector table. Interrupt requests are synchronized internally, and can be edge-triggered or level-triggered. To guarantee interrupt recognition, the requesting device must continue asserting INT4 until the request is acknowledged.
MCS2-MCS0 (MCS2/PIO24, MCS1/PIO15, MCS0/PIO14)
Midrange Memory Chip Selects (output, synchronous, internal pullup) These pins indicate to the system that a memory access is in progress to the corresponding region of the midrange memory block. The base address and size of the midrange memory block are programmable. MCS2-MCS0 are held High during a bus hold condition. In addition, they have weak internal pullup resistors that are active during reset.
LCS/ONCE0
Lower Memory Chip Select (output, synchronous, internal pullup) ONCE Mode Request 0 (input) LCS--This pin indicates to the system that a memory access is in progress to the lower memory block. The base address and size of the lower memory block are programmable up to 512 Kbytes. LCS is held High during a bus hold condition. ONCE0--During reset this pin and ONCE1 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode; otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE0 has a weak internal pullup resistor that is active only during reset. This pin is not three-stated during a bus hold condition.
NMI
Nonmaskable Interrupt (input, synchronous, edgesensitive) This pin indicates to the microcontroller that an interrupt request has occurred. The NMI signal is the highest priority hardware interrupt and, unlike the INT4- INT0 pins, cannot be masked. The microcontroller always transfers program execution to the location specified by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI is asserted. Although NMI is the highest priority interrupt source, it does not participate in the priority resolution process of the maskable interrupts. There is no bit associated with NMI in the interrupt in-service or interrupt request registers. This means that a new NMI request can interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF (interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI interrupt service routine, via the STI instruction for example, the fact that an NMI is currently in service will not have any
28
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY effect on the priority resolution of maskable interrupt requests. For this reason, it is strongly advised that the interrupt service routine for NMI does not enable the maskable interrupts. An NMI transition from Low to High is latched and synchronized internally, and it initiates the interrupt at the next instruction boundary. To guarantee that the interrupt is recognized, the NMI pin must be asserted for at least one CLKOUTA period. dress bit 1 to the system. During a bus hold condition, A1 retains its previously latched value.
PCS6/A2/PIO2
Peripheral Chip Select 6 (output, synchronous) Latched Address Bit 2 (output, synchronous) PCS6--This pin indicates to the system that a memory access is in progress to the seventh region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS6 is held High during a bus hold condition or reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A2--When the EX bit in the MCS and PCS Auxiliary Register is 0, this pin supplies an internally latched address bit 2 to the system. During a bus hold condition, A2 retains its previously latched value.
PCS3-PCS0 (PCS3/PIO19, PCS2/PIO18, PCS1/PIO17, PCS0/PIO16)
Peripheral Chip Selects (output, synchronous) These pins indicate to the system that a memory access is in progress to the corresponding region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS3-PCS0 are held High during a bus hold condition. They are also held High during reset. PCS4 is not available on the Am186EM and AM188EM microcontrollers. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers.
PIO31-PIO0 (Shared)
Programmable I/O Pins (input/output, asynchronous, open-drain) The Am186EM and AM188EM microcontrollers provide 32 individually programmable I/O pins. Each PIO can be programmed with the following attributes: PIO function (enabled/disabled), direction (input/output), and weak pullup or pulldown. The pins that are multiplexed with PIO31-PIO0 are listed in Table 2 and Table 3. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 lists the defaults for the PIOs. The system initialization code must reconfigure any PIOs as required. The A19-A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset.
PCS5/A1/PIO3
Peripheral Chip Select 5 (output, synchronous) Latched Address Bit 1 (output, synchronous) PCS5--This pin indicates to the system that a memory access is in progress to the sixth region of the peripheral memory block (either I/O or memory address space). The base address of the peripheral memory block is programmable. PCS5 is held High during a bus hold condition. It is also held High during reset. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers. A1--When the EX bit in the MCS and PCS auxiliary register is 0, this pin supplies an internally latched ad-
Am186/188EM and Am186/188EMLV Microcontrollers
29
PRELIMINARY Table 2. Numeric PIO Pin Assignments
PIO No 0 1 2 3 4 5 6 7(1) 8(1) 9
(1)
Table 3.
Alphabetic PIO Pin Assignments
PIO No 7 8 9 5 12 13 4 31 30 14 15 24 25 16 17 18 19 3 2 28 29 20 21 22 23 6 11 0 10 1 27 26 Power-On Reset Status Normal operation(3) Normal operation(3) Normal operation(3) Normal operation(3) Input with pullup Input with pullup Normal operation(3) Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Normal operation(4) Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup
Associated Pin TMRIN1 TMROUT1 PCS6/A2 PCS5/A1 DT/R DEN SRDY A17 A18 A19 TMROUT0 TMRIN0 DRQ0 DRQ1 MCS0 MCS1 PCS0 PCS1 PCS2 PCS3 SCLK SDATA SDEN0 SDEN1 MCS2 MCS3/RFSH UZI TXD RXD S6/CLKDIV2 INT4 INT2
Power-On Reset Status Input with pullup Input with pulldown Input with pullup Input with pullup Normal operation(3) Normal operation Normal operation
(3) (4)
Associated Pin A17(1) A18(1) A19(1) DEN DRQ0 DRQ1 DT/R INT2 INT4 MCS0 MCS1 MCS2 MCS3/RFSH PCS0 PCS1 PCS2 PCS3 PCS5/A1 PCS6/A2 RXD S6/CLKDIV2(1,2) SCLK SDATA SDEN0 SDEN1 SRDY TMRIN0 TMRIN1 TMROUT0 TMROUT1 TXD UZI(1,2)
Normal operation(3) Normal operation(3) Normal operation
(3)
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26(1,2) 27 28 29(1,2) 30 31
Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pulldown Input with pulldown Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup Input with pullup
Notes:
1. These pins are used by emulators. (Emulators also use S2-S0, RES, NMI, CLKOUTA, BHE, ALE, AD15-AD0, and A16-A0.) 2. These pins revert to normal operation if BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available.
Notes:
1. These pins are used by emulators. (Emulators also use S2-S0, RES, NMI, CLKOUTA, BHE, ALE, AD15-AD0, and A16-A0.) 2. These pins revert to normal operation if BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset. 3. When used as a PIO, input with pullup option available. 4. When used as a PIO, input with pulldown option available.
30
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
RD
Read Strobe (output, synchronous, three-state) This pin indicates to the system that the microcontroller is performing a memory or I/O read cycle. RD is guaranteed not to be asserted before the address and data bus is floated during the address-to-data transition. RD floats during a bus hold condition.
RXD/PIO28
Receive Data (input, asynchronous) This pin supplies asynchronous serial receive data from the system to the internal UART of the microcontroller.
S2-S0
Bus Cycle Status (output, three-state, synchronous) These pins indicate to the system the type of bus cycle in progress. S2 can be used as a logical memory or I/O indicator, and S1 can be used as a data transmit or receive indicator. S2-S0 float during bus hold and hold acknowledge conditions. The S2-S0 pins are encoded as shown in Table 4.
RES
Reset (input, asynchronous, level-sensitive) This pin requires the microcontroller to perform a reset. When RES is asserted, the microcontroller immediately terminates its present activity, clears its internal logic, and CPU control is transferred to the reset address FFFF0h. RES must be held Low for at least 1 ms. RES can be asserted asynchronously to CLKOUTA because RES is synchronized internally. For proper initialization, VCC must be within specifications, and CLKOUTA must be stable for more than four CLKOUTA periods during which RES is asserted. The microcontroller begins fetching instructions approximately 6.5 CLKOUTA periods after RES is deasserted. This input is provided with a Schmitt trigger to facilitate power-on RES generation via an RC network.
Table 4.
S2 0 0 0 0 1 1 1 1 S1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Bus Cycle Encoding
Bus Cycle Interrupt acknowledge Read data from I/O Write data to I/O Halt Instruction fetch Read data from memory Write data to memory None (passive)
S0
RFSH2/ADEN (AM188EM Microcontroller Only)
Refresh 2 (three-state, output, synchronous) Address Enable (input, internal pullup) RFSH2--Asserted Low to signify a DRAM refresh bus cycle. The use of RFSH2/ADEN to signal a refresh is not valid when PSRAM mode is selected. Instead, the MCS3/RFSH signal is provided to the PSRAM. ADEN--If RFSH2/ADEN is held High or left floating on power-on reset, the AD bus (AO15-AO8 and AD7- AD0) is enabled or disabled during the address portion of LCS and UCS bus cycles based on the DA bit in the LMCS and UMCS registers. If the DA bit is set, the memory address is accessed on the A19-A0 pins. This mode of operation reduces power consumption. For more information, see the "Bus Operation" section on page 37. There is a weak internal pullup resistor on RFSH2/ADEN so no external pullup is required. If RFSH2/ADEN is held Low on power-on reset, the AD bus drives both addresses and data regardless of the DA bit setting. The pin is sampled one crystal clock cycle after the rising edge of RES. RFSH2/ADEN is three-stated during bus holds and ONCE mode.
S6/CLKDIV2/PIO29
Bus Cycle Status Bit 6 (output, synchronous) Clock Divide by 2 (input, internal pullup) S6--During the second and remaining periods of a cycle (t2, t3, and t4), this pin is asserted High to indicate a DMA-initiated bus cycle. During a bus hold or reset condition, S6 floats. CLKDIV2--If S6/CLKDIV2/PIO29 is held Low during power-on reset, the chip enters clock divided by 2 mode where the processor clock is derived by dividing the external clock input by 2. If this mode is selected, the PLL is disabled. The pin is sampled on the rising edge of RES. If S6 is to be used as PIO29 in input mode, the device driving PIO29 must not drive the pin Low during poweron reset. S6/CLKDIV2/PIO29 defaults to a PIO input with pullup, so the pin does not need to be driven High externally.
Am186/188EM and Am186/188EMLV Microcontrollers
31
PRELIMINARY
SCLK/PIO20
Serial Clock (output, synchronous) This pin supplies the synchronous serial interface (SSI) clock to a slave device, allowing transmit and receive operations to be synchronized between the microcontroller and the slave. SCLK is derived from the microcontroller internal clock and then divided by 2, 4, 8, or 16 depending on register settings. An access to any of the SSR or SSD registers activates SCLK for eight SCLK cycles (see Figure 11 and Figure 12 on page 49). When SCLK is inactive, it is held High by the microcontroller.
TMRIN1/PIO0
Timer Input 1 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 1. After internally synchronizing a Low-to-High transition on TMRIN1, the microcontroller increments the timer. TMRIN1 must be tied High if not being used.
TMROUT0/PIO10
Timer Output 0 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT0 is floated during a bus hold or reset.
SDATA/PIO21
Serial Data (input/output, synchronous) This pin transmits synchronous serial interface (SSI) data to and from a slave device. When SDATA is inactive, a weak keeper holds the last value of SDATA on the pin.
TMROUT1/PIO1
Timer Output 1 (output, synchronous) This pin supplies the system with either a single pulse or a continuous waveform with a programmable duty cycle. TMROUT1 can also be programmed as a watchdog timer. TMROUT1 is floated during a bus hold or reset.
SDEN1/PIO23, SDEN0/PIO22
Serial Data Enables (output, synchronous) These pins enable data transfers on port 1 and port 0 of the synchronous serial interface (SSI). The microcontroller asserts either SDEN1 or SDEN0 at the beginning of a transfer and deasserts it after the transfer is complete. When SDEN1-SDEN0 are inactive, they are held Low by the microcontroller.
TXD/PIO27
Transmit Data (output, asynchronous) This pin supplies asynchronous serial transmit data to the system from the internal UART of the microcontroller.
UCS/ONCE1
Upper Memory Chip Select (output, synchronous) ONCE Mode Request 1 (input, internal pullup) UCS--This pin indicates to the system that a memory access is in progress to the upper memory block. The base address and size of the upper memory block are programmable up to 512 Kbytes. UCS is held High during a bus hold condition. After power-on reset, UCS is asserted because the processor begins executing at FFFF0h and the default configuration for the UCS chip select is 64 Kbytes from F0000h to FFFFFh. ONCE1--During reset, this pin and ONCE0 indicate to the microcontroller the mode in which it should operate. ONCE0 and ONCE1 are sampled on the rising edge of RES. If both pins are asserted Low, the microcontroller enters ONCE mode. Otherwise, it operates normally. In ONCE mode, all pins assume a high-impedance state and remain in that state until a subsequent reset occurs. To guarantee that the microcontroller does not inadvertently enter ONCE mode, ONCE1 has a weak internal pullup resistor that is active only during a reset. This pin is not three-stated during a bus hold condition.
SRDY/PIO6
Synchronous Ready (input, synchronous, level-sensitive) This pin indicates to the microcontroller that the addressed memory space or I/O device will complete a data transfer. The SRDY pin accepts an active High input synchronized to CLKOUTA. Using SRDY instead of ARDY allows a relaxed system timing because of the elimination of the one-half clock period required to internally synchronize ARDY. To always assert the ready condition to the microcontroller, tie SRDY High. If the system does not use SRDY, tie the pin Low to yield control to ARDY.
TMRIN0/PIO11
Timer Input 0 (input, synchronous, edge-sensitive) This pin supplies a clock or control signal to the internal microcontroller timer 0. After internally synchronizing a Low-to-High transition on TMRIN0, the microcontroller increments the timer. TMRIN0 must be tied High if not being used.
32
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
UZI/PIO26
Upper Zero Indicate (output, synchronous) UZI--This pin lets the designer determine if an access to the interrupt vector table is in progress by ORing it with bits 15-10 of the address and data bus (AD15- AD10 on the 186 and AO15-AO10 on the 188). UZI is the logical OR of the inverted A19-A16 bits, and it asserts in the first period of a bus cycle and is held throughout the cycle. This signal should be pulled High or allowed to float at reset. If this pin is Low at the negation of reset, the Am186EM and AM188EM microcontrollers will enter a reserved clock test mode.
X1
Crystal Input (input) This pin and the X2 pin provide connections for a fundamental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, connect the source to the X1 pin and leave the X2 pin unconnected.
X2
Crystal Output (output) This pin and the X1 pin provide connections for a fundamental mode or third-overtone parallel-resonant crystal used by the internal oscillator circuit. To provide the microcontroller with an external clock source, leave the X2 pin unconnected and connect the source to the X1 pin.
VCC
Power Supply (input) These pins supply power (+5 V) to the microcontroller.
WHB (Am186EM Microcontroller Only)
Write High Byte (output, three-state, synchronous) This pin and WLB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WHB is asserted with AD15-AD8. WHB is the logical OR of BHE and WR. This pin floats during reset.
WLB (Am186EM Microcontroller Only) WB (AM188EM Microcontroller Only)
Write Low Byte (output, three-state, synchronous) Write Byte (output, three-state, synchronous) WLB--This pin and WHB indicate to the system which bytes of the data bus (upper, lower, or both) participate in a write cycle. In 80C186 designs, this information is provided by BHE, AD0, and WR. However, by using WHB and WLB, the standard system interface logic and external address latch that were required are eliminated. WLB is asserted with AD7-AD0. WLB is the logical OR of AD0 and WR. This pin floats during reset. WB--On the AM188EM microcontroller, this pin indicates a write to the bus. WB uses the same early timing as the nonmultiplexed address bus. WB is associated with AD7-AD0. This pin floats during reset.
WR
Write Strobe (output, synchronous) This pin indicates to the system that the data on the bus is to be written to a memory or I/O device. WR floats during a bus hold or reset condition.
Am186/188EM and Am186/188EMLV Microcontrollers
33
PRELIMINARY
FUNCTIONAL DESCRIPTION
AMD's Am186 and Am188 family of microcontrollers and microprocessors is based on the architecture of the original 8086 and 8088 microcontrollers and currently includes the 80C186, 80C188, 80L186, 80L188, Am186EM, AM188EM, Am186EMLV, AM188EMLV, Am186ES, Am188ES, Am186ESLV, Am188ESLV, Am186ER, and Am188ER microcontrollers. All family members contain the same basic set of registers, instructions, and addressing modes and are compatible with the industry-standard 80C186/188 microcontrollers. A full description of all the Am186EM and AM188EM microcontroller registers is included in the Am186EM and AM188EM Microcontrollers User's Manual, order# 19713. The instruction set for the Am186EM and AM188EM microcontrollers is documented in the Am186 and Am188 Family Instruction Set Manual, order# 21267.
1 19 0 0 15 2 0 2 2 A Shift Left 4 Bits
1 15 0 15
2
A
0
2
4 Segment Logical 0 Base Address 2 Offset 0
4
0 0 2 0 2 0 Physical Address
1 19
A
6
To Memory
Memory Organization
Memory is organized in sets of segments. Each segment is a linear contiguous sequence of 64K (216) 8-bit bytes. Memory is addressed using a two-component address that consists of a 16-bit segment value and a 16-bit offset. The 16-bit segment values are contained in one of four internal segment registers (CS, DS, SS, or ES). The physical address is calculated by shifting the segment value left by 4 bits and adding the 16-bit offset value to yield a 20-bit physical address (see Figure 3). This allows for a 1-Mbyte physical address size. All instructions that address operands in memory must specify the segment value and the 16-bit offset value. For speed and compact instruction encoding, the segment register used for physical address generation is implied by the addressing mode used (see Table 5).
Figure 2. Two-Component Address
I/O Space
The I/O space consists of 64K 8-bit or 32K 16-bit ports. Separate instructions (IN, INS and OUT, OUTS) address the I/O space with either an 8-bit port address specified in the instruction, or a 16-bit port address in the DX register. Eight-bit port addresses are zero-extended so that A15-A8 are Low. I/O port addresses 00F8h through 00FFh are reserved. The Am186EM and AM188EM microcontrollers provide specific instructions for addressing I/O space.
Table 5.
Memory Reference Needed Instructions Local Data Stack External Data (Global)
Segment Register Selection Rules
Implicit Segment Selection Rule Instructions (including immediate data) All data references All stack pushes and pops; any memory references that use BP Register All string instruction references that use the DI Register as an index
Segment Register Used Code (CS) Data (DS) Stack (SS) Extra (ES)
34
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
BUS OPERATION
The industry-standard 80C186 and 80C188 microcontrollers use a multiplexed address and data (AD) bus. The address is present on the AD bus only during the t1 clock phase. The Am186EM and AM188EM microcontrollers continue to provide the multiplexed AD bus and, in addition, provide a nonmultiplexed address (A) bus. The A bus provides an address to the system for the complete bus cycle (t1-t4). For systems where power consumption is a concern, it is possible to disable the address from being driven on the AD bus on the Am186EM microcontroller and on the AD and AO buses on the AM188EM microcontroller during the normal address portion of the bus cycle for accesses to UCS and/or LCS address spaces. In this mode, the affected bus is placed in a high impedance state during the address portion of the bus cycle. This feature is enabled through the DA bits in the UMCS and LMCS registers. When address disable is in effect, the number of signals that assert on the bus during all normal bus cycles to the associated address space is reduced, decreasing power consumption and reducing processor switching noise. On the AM188EM microcontroller, the address is driven on A015-A08 during the data portion of the bus cycle, regardless of the setting of the DA bits. If the ADEN pin is pulled Low during processor reset, the value of the DA bits in the UMCS and LMCS registers is ignored and the address is driven on the AD bus for all accesses, thus preserving the industry-standard 80C186 and 80C188 microcontrollers' multiplexed address bus and providing support for existing emulation tools. The following diagrams show the Am186EM and AM188EM microcontroller bus cycles when the address bus disable feature is in effect. Figure 3 shows the affected signals during a normal read or write operation for an Am186EM microcontroller. The address and data will be multiplexed onto the AD bus. Figure 4 shows an Am186EM microcontroller bus cycle when address bus disable is in effect. This results in having the AD bus operate in a nonmultiplexed address/data mode. The A bus will have the address during a read or write operation. Figure 5 shows the affected signals during a normal read or write operation for an AM188EM microcontroller. The multiplexed address/data mode is compatible with the 80C186 and 80C188 microcontrollers and might be used to take advantage of existing logic or peripherals. Figure 6 shows an AM188EM microcontroller bus cycle when address bus disable is in effect. The address and data is not multiplexed. The AD7-AD0 signals will have only data on the bus, while the AO bus will have the address during a read or write operation.
t1 Address Phase
t2
t3 Data Phase
t4
CLKOUTA A19-A0 Address
AD15-AD0 (Read)
Address
Data
AD15-AD0 (Write) LCS or UCS
Address
Data
MCSx, PCSx
Figure 3.
Am186EM Microcontroller Address Bus--Normal Read and Write Operation
Am186/188EM and Am186/188EMLV Microcontrollers
35
PRELIMINARY
t1 Address Phase CLKOUTA A19-A0 AD7-AD0 (Read) AD15-AD8 (Read) AD15-AD0 (Write) LCS, UCS
t2
t3 Data Phase
t4
Address
Data Data
Data
Figure 4.
Am186EM Microcontroller--Read and Write with Address Bus Disable In Effect
t1 Address Phase
t2
t3 Data Phase
t4
CLKOUTA A19-A0 Address
AD7-AD0 (Read)
Address
Data
AO15-AO8 (Read or Write) AD7-AD0 (Write) LCS or UCS
Address
Address
Data
MCSx, PCSx
Figure 5.
AM188EM Microcontroller Address Bus--Normal Read and Write Operation
36
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
t1 Address Phase CLKOUTA A19-A0 AD7-AD0 (Read)
t2
t3 Data Phase
t4
Address
Data
AO15-AO8 AD7-AD0 (Write) LCS, UCS
Address
Data
Figure 6.
AM188EM Microcontroller--Read and Write with Address Bus Disable In Effect
BUS INTERFACE UNIT
The bus interface unit controls all accesses to external peripherals and memory devices. External accesses include those to memory devices, as well as those to memory-mapped and I/O-mapped peripherals and the p er i p h e r a l c o n tr o l b l o c k . T h e A m 1 8 6 E M a nd AM188EM microcontrollers provide an enhanced bus interface unit with the following features: n A nonmultiplexed address bus n Separate byte write enables for high and low bytes in the Am186EM microcontroller only n Pseudo Static RAM (PSRAM) support The standard 80C186/188 multiplexed address and data bus requires system interface logic and an external address latch. On the Am186EM and AM188EM microcontrollers, new byte write enables, PSRAM control logic, and a new nonmultiplexed address bus can reduce design costs by eliminating this external logic.
Byte Write Enables
The Am186EM microcontroller provides the WHB (Write High Byte) and WLB (Write Low Byte) signals, which act as byte write enables. WHB is the logical OR of BHE and WR. WHB is Low when BHE and WR are both Low. WLB is the logical OR of AD0 and WR. WLB is Low when AD0 and WR are both Low. WB is Low whenever a byte is written on the AM188EM microcontroller. The byte write enables are driven in conjunction with the nonmultiplexed address bus as required for the write timing requirements of common SRAMs.
Nonmultiplexed Address Bus
The nonmultiplexed address bus (A19-A0) is valid one-half CLKOUTA cycle in advance of the address on the AD bus. When used in conjunction with the modified UCS and LCS outputs and the byte write enable signals, the A19-A0 bus provides a seamless interface to SRAM, PSRAM, and Flash/EPROM memory systems.
Am186/188EM and Am186/188EMLV Microcontrollers
37
PRELIMINARY
Pseudo Static RAM (PSRAM) Support
The Am186EM and AM188EM microcontrollers support the use of PSRAM devices in low memory chip-select (LCS) space only. When PSRAM mode is enabled, the timing for the LCS signal is modified by the chip-select control unit to provide a CS precharge period during PSRAM accesses. The 40-MHz timing of the Am186EM and AM188EM microcontrollers is appropriate to allow 70-ns PSRAM to run with one wait state. PSRAM mode is enabled through a bit in the Low Memory Chip-Select (LMCS) Register. The PSRAM feature is disabled on CPU reset. In addition to the LCS timing changes for PSRAM precharge, the PSRAM devices also require periodic refresh of all internal row addresses to retain their data. Although refresh of PSRAM can be accomplished several ways, the Am186EM and AM188EM microcontrollers implement auto refresh only. The Am186EM and AM188EM microcontrollers generate RFSH, a refresh signal, to the PSRAM devices when PSRAM mode is enabled. No refresh address is required by the PSRAM when using the auto refresh mechanism. The RFSH signal is multiplexed with the MCS3 signal pin. When PSRAM mode is enabled, MCS3 is not available for use as a chip-select signal. The refresh control unit must be programmed before accessing PSRAM in LCS space. The refresh counter in the Clock Prescaler (CDRAM) Register must be configured with the required refresh interval value. The ending address of LCS space and the ready and waitstate generation in the LMCS Register must also be programmed. The refresh counter reload value in the CDRAM Register should not be set to less than 18 (12h) in order to provide time for processor cycles within refresh. The refresh address counter must be set to 000000h to prevent another chip select from asserting. LCS is held High during a refresh cycle. The A bus is not used during refresh cycles. The LMCS Register must be configured to external ready ignored (R2=1) with one wait state (R1-R0=01b), and the PSRAM mode enable bit (SE) must be set.
PERIPHERAL CONTROL BLOCK (PCB)
The integrated peripherals of the Am186EM and AM188EM microcontrollers are controlled by 16-bit read/write registers. The peripheral registers are contained within an internal 256-byte control block. The registers are physically located in the peripheral devices they control, but they are addressed as a single 256-byte block. Figure 7 shows a map of these registers.
Reading and Writing the PCB
Code that is intended to execute on the AM188EM microcontroller should perform all writes to the PCB registers as byte writes. These writes will transfer 16 bits of data to the PCB register even if an 8-bit register is named in the instruction. For example, out dx, al results in the value of ax being written to the port address in dx. Reads to the PCB should be done as word reads. Code written in this manner will run correctly on the AM188EM microcontroller and on the Am186EM microcontroller. Unaligned reads and writes to the PCB result in unpredi cta ble beh av ior on both the A m18 6E M an d AM188EM microcontrollers. For a complete description of all the registers in the PCB, see the Am186EM and AM188EM Microcontrollers User's Manual, order# 19713.
38
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Offset (Hexadecimal) FE w F6 F4 F0 w E4 E2 E0 w DA D8 D6 D4 D2 D0 CA C8 C6 C4 C2 C0 w A8 A6 A4 A2 A0 88 86 84 82 80 w
Register Name Peripheral Control Block Relocation Register w Reset Configuration Register Processor Release Level Register PDCON Register w Enable RCU Register Clock Prescaler Register Memory Partition Register w DMA 1 Control Register DMA 1 Transfer Count Register DMA 1 Destination Address High Register DMA 1 Destination Address Low Register DMA 1 Source Address High Register DMA 1 Source Address Low Register DMA 0 Control Register DMA 0 Transfer Count Register DMA 0 Destination Address High Register DMA 0 Destination Address Low Register DMA 0 Source Address High Register DMA 0 Source Address Low Register w PCS and MCS Auxiliary Register Midrange Memory Chip Select Register Peripheral Chip Select Register Low Memory Chip Select Register Upper Memory Chip Select Register w Serial Port Baud Rate Divisor Register Serial Port Receive Register Serial Port Transmit Register Serial Port Status Register Serial Port Control Register
Changed from 80C186 microcontroller. Note: Gaps in offset addresses indicate reserved registers.
Figure 7.
Peripheral Control Block Register Map
Am186/188EM and Am186/188EMLV Microcontrollers
39
PRELIMINARY
Offset (Hexadecimal) 7A 78 76 74 72 70
w
Register Name PIO Data 1 Register PIO Direction 1 Register PIO Mode 1 Register PIO Data 0 Register PIO Direction 0 Register PIO Mode 0 Register
w
w 66 62 60 5E 5C 5A 58 56 54 52 50 w 44 42 40 3E 3C 3A 38 36 34 32 30 2E 2C 2A 28 26 24 22 20 18 16 14 12 10 Serial Port Interrupt Control Register Watchdog Timer Control Register INT4 Control Register INT3 Control Register INT2 Control Register INT1 Control Register INT0 Control Register DMA 1 Interrupt Control Register DMA 0 Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register In-service Register Priority Mask Register Interrupt Mask Register Poll Status Register Poll Register End-of-Interrupt Register Interrupt Vector Register Synchronous Serial Receive Register Synchronous Serial Transmit 0 Register Synchronous Serial Transmit 1 Register Synchronous Serial Enable Register Synchronous Serial Status Register Timer 2 Mode/Control Register Timer 2 Maxcount Compare A Register Timer 2 Count Register Timer 1 Mode/Control Register Timer 1 Maxcount Compare B Register Timer 1 Maxcount Compare A Register Timer 1 Count Register Timer 0 Mode/Control Register Timer 0 Maxcount Compare B Register Timer 0 Maxcount Compare A Register Timer 0 Count Register
w
w
Changed from 80C186 microcontroller. Note: Gaps in offset addresses indicate reserved registers.
Figure 7.
Peripheral Control Block Register Map (continued)
40
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
CLOCK AND POWER MANAGEMENT
The clock and power management unit of the Am186EM and AM188EM microcontrollers includes a phase-locked loop (PLL) and a second programmable system clock output (CLKOUTB). fect the operation of the clock generator. Values for the loading on X1 and X2 must be chosen to provide the necessary phase shift and crystal operation. Selecting a Crystal When selecting a crystal, the load capacitance should always be specified (CL). This value can cause variance in the oscillation frequency from the desired specified value (resonance). The load capacitance and the loading of the feedback network have the following relationship: CL = (C1 C2) + CS (C1 + C2)
Phase-Locked Loop (PLL)
In a traditional 80C186/188 design, the crystal frequency is twice that of the desired internal clock. Because of the internal PLL on the Am186EM and AM188EM microcontrollers, the internal clock generated by the Am186EM and AM188EM microcontrollers (CLKOUTA) is the same frequency as the crystal. The PLL takes the crystal inputs (X1 and X2) and generates a 45/55% (worst case) duty cycle intermediate system clock of the same frequency. This removes the need for an external 2x oscillator, reducing system cost. The PLL is reset by an on-chip power-on reset (POR) circuit.
Crystal-Driven Clock Source
The internal oscillator circuit of the Am186EM and AM188EM microcontrollers is designed to function with a parallel-resonant fundamental or third-overtone crystal. Because of the PLL, the crystal frequency should be equal to the processor frequency. Do not replace a crystal with an LC or RC equivalent. The signals X1 and X2 are connected to an internal inverting amplifier (oscillator) which provides, along with the external feedback loading, the necessary phase shift (Figure 8). In such a positive feedback circuit, the inverting amplifier has an output signal (X2) 180 degrees out of phase of the input signal (X1). The external feedback network provides an additional 180-degree phase shift. In an ideal system, the input to X1 will have 360 or zero degrees of phase shift. The external feedback network is designed to be as close to ideal as possible. If the feedback network is not providing necessary phase shift, negative feedback will dampen the output of the amplifier and negatively af-
where CS is the stray capacitance of the circuit. Placing the crystal and CL in series across the inverting amplifier and tuning these values (C1, C2) allows the crystal to oscillate at resonance. This relationship is true for both fundamental and third-overtone operation. Finally, there is a relationship between C1 and C2. To enhance the oscillation of the inverting amplifier, these values need to be offset with the larger load on the output (X2). Equal values of these loads will tend to balance the poles of the inverting amplifier. The characteristics of the inverting amplifier set limits on the following parameters for crystals: ESR (Equivalent Series Resistance)........... 80 ohm max Drive Level.....................................................................................1 mW max The recommended range of values for C1 and C2 are as follows: C1 ..............................................................................................................15 pF 20% C2 ..............................................................................................................22 pF 20% The specific values for C1 and C2 must be determined by the designer and are dependent on the characteristics of the chosen crystal and board design.
C1 X1 Crystal Crystal C1 C2 X2 C2 Note 1 Am186EM Microcontroller
a. Inverting Amplifier Configuration
Note 1: Use for Third Overtone Mode XTAL Frequency L1 Value (Max) 20 MHz 12 H 20% 25 MHz 8.2 H 20% 33 MHz 4.7 H 20% 40 MHz 3.0 H 20%
200 pF b. Crystal Configuration
Figure 8.
Am186EM and AM188EM Microcontrollers Oscillator Configurations Am186/188EM and Am186/188EMLV Microcontrollers 41
PRELIMINARY
External Source Clock
Alternately, the internal oscillator can be driven from an external clock source. This source should be connected to the input of the inverting amplifier (X1), with the output (X2) not connected.
CLKOUTB operate at either the processor frequency or the crystal input frequency. The output drivers for both clocks are individually programmable for disable. Figure 9 shows the organization of the clocks. The second clock output (CLKOUTB) allows one clock to run at the crystal input frequency and the other clock to run at the power-save frequency. Individual drive enable bits allow selective enabling of just one or both of these clock outputs.
System Clocks
The base system clock of the 80C186 and 80C188 microcontrollers is renamed CLKOUTA and the additional output is called CLKOUTB. CLKOUTA and
Processor Internal Clock PLL X1, X2 Power-Save Divisor (/2 to /128)
Mux Drive Enable Time Delay 6 2.5ns Drive Enable
CLKOUTA
Mux
CLKOUTB
Figure 9.
Clock Organization
Power-Save Operation
The power-save mode of the Am186EM and AM188EM microcontrollers reduces power consumption and heat dissipation, thereby extending battery life in portable systems. In power-save mode, operation of the CPU and internal peripherals continues at a slower clock frequency. When an interrupt occurs, the microcontroller automatically returns to its normal operating frequency on the internal clock's next rising edge of t3. In order for an interrupt to be recognized, it must be valid before the internal clock's rising edge of t3.
After RES becomes inactive and an internal processing interval elapses, the microcontroller begins execution with the instruction at physical location FFFF0h. RES also sets some registers to predefined values.
The Reset Configuration Register
When the RES input is asserted Low, the contents of the address/data bus (AD15-AD0) are written into the Reset Configuration register. The system can place configuration information on the address/data bus using weak external pullup or pulldown resistors, or using an external driver that is enabled during reset. The processor does not drive the address/data bus during reset. For example, the Reset Configuration register could be used to provide the software with the position of a configuration switch in the system. Using weak external pullup and pulldown resistors on the address and data bus, the system would provide the microcontroller with a value corresponding to the position of the jumper during a reset.
Note: Power-save operation requires that clock-dependent devices be reprogrammed for clock frequency changes. Software drivers must be aware of clock frequency.
Initialization and Processor Reset
Processor initialization or startup is accomplished by driving the RES input pin Low. RES must be held Low for 1 ms during power-up to ensure proper device initialization. RES forces the Am186EM and AM188EM microcontrollers to terminate all execution and local bus activity. No instruction or bus activity occurs as long as RES is active.
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Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
CHIP-SELECT UNIT
The Am186EM and AM188EM microcontrollers contain logic that provides programmable chip-select generation for both memories and peripherals. The logic can be programmed to provide ready and wait-state generation and latched address bits A1 and A2. The chip-select lines are active for all memory and I/O cycles in their programmed areas, whether they are generated by the CPU or by the integrated DMA unit. The Am186EM and AM188EM microcontrollers provide six chip-select outputs for use with memory devices and six more for use with peripherals in either memory space or I/O space. The six chip selects for memory devices can be used to address three memory ranges. Each of the six peripheral chip selects addresses a 256-byte block that is offset from a programmable base address. A read or write access to the corresponding chip select register activates the chip selects.
Chip-Select Overlap
Although programming the various chip selects on the Am186EM and AM188EM microcontrollers so that multiple chip select signals are asserted for the same physical address is not recommended, it may be unavoidable in some systems. In such systems, the chip selects whose assertions overlap must have the same configuration for ready (external ready required or not required) and the number of wait states to be inserted into the cycle by the processor. The peripheral control block (PCB) is accessed using internal signals. These internal signals function as chip selects configured with zero wait states and no external ready. Therefore, the PCB can be programmed to addresses that overlap external chip select signals if those external chip selects are programmed to zero wait states with no external ready required. When overlapping an additional chip select with either the LCS or UCS chip selects, it must be noted that setting the Disable Address (DA) bit in the LMCS or UMCS register will disable the address from being driven on the AD bus for all accesses for which the associated chip select is asserted, including any accesses for which multiple chip selects assert. The MCS and PCS chip select pins can be configured as either chip selects (normal function) or as PIO inputs or outputs. It should be noted; however, that the ready and wait state generation logic for these chip selects is in effect regardless of their configurations as chip selects or PIOs. This means that if these chip selects are enabled (by a read or write to the MMCS and MPCS for the MCS chip selects, or by a read or write to the PACS and MPCS registers for the PCS chip selects), the ready and wait state programming for these signals must agree with the programming for any other chip selects with which their assertion would overlap if they were configured as chip selects. Although the PCS4 signal is not available on an external pin, the ready and wait state logic for this signal still exists internal to the part. For this reason, the PCS4 address space must follow the rules for overlapping chip selects. The ready and wait-state logic for PCS6- PCS5 is disabled when these signals are configured as address bits A2-A1. Failure to configure overlapping chip selects with the same ready and wait state requirements may cause the processor to hang with the appearance of waiting for a ready signal. This behavior may occur even in a system in which ready is always asserted (ARDY or SRDY tied High).
Chip-Select Timing
The timing for the UCS and LCS outputs is modified from the original 80C186 microcontroller. These outputs now assert in conjunction with the nonmultiplexed address bus for normal memory timing. To allow these outputs to be available earlier in the bus cycle, the number of programmable memory size selections has been reduced.
Ready and Wait-State Programming
The Am186EM and AM188EM microcontrollers can be programmed to sense a ready signal for each of the peripheral or memory chip-select lines. The ready signal can be either the ARDY or SRDY signal. Each chip-select control register (UMCS, LMCS, MMCS, PACS, and MPCS) contains a single-bit field that determines whether the external ready signal is required or ignored. The number of wait states to be inserted for each access to a peripheral or memory region is programmable. The chip-select control registers for UCS, LCS, MCS3-MCS0, PCS6, and PCS5 contain a two-bit field that determines the number of wait states from zero to three to be inserted. PCS3-PCS0 use three bits to provide additional values of 5, 7, 9, and 15 wait states. When external ready is required, internally programmed wait states will always complete before external ready can terminate or extend a bus cycle. For example, if the internal wait states are set to insert two wait states, the processor samples the external ready pin during the first wait cycle. If external ready is asserted at that time, the access completes after six cycles (four cycles plus two wait states). If external ready is not asserted during the first wait state, the access is extended until ready is asserted, which is followed by one more wait state followed by t4.
Am186/188EM and Am186/188EMLV Microcontrollers
43
PRELIMINARY Configuring PCS in I/O space with LCS or any other chip select configured for memory address 0 is not considered overlapping of the chip selects. Overlapping chip selects refers to configurations where more than one chip select asserts for the same physical address.
Midrange Memory Chip Selects
The Am186EM and AM188EM microcontrollers provide four chip selects, MCS3-MCS0, for use in a userlocatable memory block. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS and LCS chip selects, as well as the address range of the Peripheral Chip Selects, PCS6, PCS5, and PCS3-PCS0, if they are mapped to memory. The MCS address range can overlap the PCS address range if the PCS chip selects are mapped to I/O space. Unlike the UCS and LCS chip selects, the MCS outputs assert with the multiplexed AD address bus.
Upper Memory Chip Select
The Am186EM and AM188EM microcontrollers provide a UCS chip select for the top of memory. On reset, the Am186EM and AM188EM microcontrollers begin fetching and executing instructions starting at memory location FFFF0h. Therefore, upper memory is usually used as instruction memory. To facilitate this usage, UCS defaults to active on reset, with a default memory range of 64 Kbytes from F0000h to FFFFFh, with external ready required and three wait states automatically inserted. The UCS memory range always ends at FFFFFh. The lower boundary is programmable.
Peripheral Chip Selects
The Am186EM and AM188EM microcontrollers provide six chip selects, PCS6-PCS5 and PCS3-PCS0, for use within a user-locatable memory or I/O block. PCS4 is not available on the Am186EM and AM188EM microcontrollers. The base address of the memory block can be located anywhere within the 1-Mbyte memory address space, exclusive of the areas associated with the UCS, LCS, and MCS chip selects, or they can be configured to access the 64 Kbyte I/O space. The PCS pins are not active on reset. PCS6-PCS5 can have from zero to three wait states. PCS3-PCS0 can have four additional wait-state values--5, 7, 9, and 15. Unlike the UCS and LCS chip selects, the PCS outputs assert with the multiplexed AD address bus. Note also that each peripheral chip select asserts over a 256-byte address range, which is twice the address range covered by peripheral chip selects in the 80C186 and 80C188 microcontrollers.
Low Memory Chip Select
The Am186EM and AM188EM microcontrollers provide an LCS chip select for the bottom of memory. Since the interrupt vector table is located at the bottom of memory starting at 00000h, the LCS pin is usually used to control data memory. The LCS pin is not active on reset.
44
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
REFRESH CONTROL UNIT
The Refresh Control Unit (RCU) automatically generates refresh bus cycles. After a programmable period of time, the RCU generates a memory read request to the bus interface unit. The RCU is fixed to three wait states for the PSRAM auto refresh mode. If the HLDA pin is active when a refresh request is generated (indicating a bus hold condition), then the Am186EM and AM188EM microcontrollers deactivate the HLDA pin in order to perform a refresh cycle. The external bus master must remove the HOLD signal for at least one clock in order to allow the refresh cycle to execute. The sequence of HLDA going inactive while HOLD is being held active can be used to signal a pending refresh request.
INTERRUPT CONTROL UNIT
The Am186EM and AM188EM microcontrollers can receive interrupt requests from a variety of sources, both internal and external. The internal interrupt controller arranges these requests by priority and presents them one at a time to the CPU. There are six external interrupt sources on the Am186EM and AM188EM microcontrollers--five maskable interrupt pins and one nonmaskable interrupt pin. In addition, there are six total internal interrupt sources--three timers, two DMA channels, and the asynchronous serial port--that are not connected to external pins. The Am186EM and AM188EM microcontrollers provide three interrupt sources not present on the Am186 and Am188 microcontrollers. The first is an additional external interrupt pin (INT4). This pin operates much like the already existing interrupt pins (INT3-INT0). The second is an internal watchdog timer interrupt. The third is an internal interrupt from the asynchronous serial port. The five maskable interrupt request pins can be used as direct interrupt requests, or they can be cascaded with an 82C59A-compatible external interrupt controller if more inputs are needed. An external interrupt contr ol l er c an be u s ed as the s ys te m m as te r by programming the internal interrupt controller to operate in slave mode. In all cases, nesting can be enabled so that interrupt service routines for lower priority interrupts are interrupted by a higher priority interrupt.
Am186/188EM and Am186/188EMLV Microcontrollers
45
PRELIMINARY
TIMER CONTROL UNIT
There are three 16-bit programmable timers in the Am186EM and AM188EM microcontrollers. Timer 0 and timer 1 are connected to four external pins (each one has an input and an output). These two timers can be used to count or time external events, or to generate nonrepetitive or variable-duty-cycle waveforms. In addition, timer 1 can be configured as a watchdog timer interrupt. The watchdog timer interrupt provides a mechanism for detecting software crashes or hangs. The TMROUT1 output is internally connected to the watchdog timer interrupt. The TIMER1 count register must then be reloaded at intervals less than the TIMER1 max count to assure the watchdog interrupt is not taken. If the code crashes or hangs, the TIMER1 countdown will cause a watchdog interrupt. Timer 2 is not connected to any external pins. It can be used for real-time coding and time-delay applications. It can also be used as a prescale to timers 0 and 1 or as a DMA request source. The timers are controlled by eleven 16-bit registers in the peripheral control block. A timer's timer-count register contains the current value of that timer. The timercount register can be read or written with a value at any time, regardless of whether the timer is running. The microcontroller increments the value of the timer-count register each time a timer event occurs. Each timer also has a maximum-count register that defines the maximum value the timer will reach. When the timer reaches the maximum value, it resets to 0 during the same clock cycle--the value in the maximum-count register is never stored in the timer-count register. Also, timers 0 and 1 have a secondary maximum-count register. Using both the primary and secondary maximum-count registers lets the timer alternate between two maximum values. If the timer is programmed to use only the primary maximum-count register, the timer output pin switches Low for one clock cycle after the maximum value is reached. If the timer is programmed to use both of its maximum-count registers, the output pin indicates which maximum-count register is currently in control, thereby creating a waveform. The duty cycle of the waveform depends on the values in the maximumcount registers. Each timer is serviced every fourth clock cycle, so a timer can operate at a speed of up to one-quarter the internal clock frequency. A timer can be clocked externally at this same frequency; however, because of internal synchronization and pipelining of the timer circuitry, the timer output may take up to six clock cycles to respond to the clock or gate input.
DIRECT MEMORY ACCESS (DMA)
Direct memory access (DMA) permits transfer of data between memory and peripherals without CPU involvement. The DMA unit in the Am186EM and AM188EM microcontrollers, shown in Figure 10, provides two high-speed DMA channels. Data transfers can occur between memory and I/O spaces (e.g., memory to I/O) or within the same space (e.g., memory-to-memory or I/O-toI/O). In addition, either bytes or words can be transferred to or from even or odd addresses on the Am186EM microcontroller. The AM188EM microcontroller does not support word transfers. Only two bus cycles (a minimum of eight clocks) are necessary for each data transfer. Each channel accepts a DMA request from one of three sources--the channel request pin (DRQ1- DRQ0), timer 2, or the system software. The channels can be programmed with different priorities in the event of a simultaneous DMA request or if there is a need to interrupt transfers on the other channel.
DMA Operation
Each channel has six registers in the peripheral control block that define specific channel operations. The DMA registers consist of a 20-bit source address (2 registers), a 20-bit destination address (2 registers), a 16-bit transfer count register, and a 16-bit control register. The DMA transfer count register (DTC) specifies the number of DMA transfers to be performed. Up to 64K byte or word transfers can be performed with automatic termination. The DMA control registers define the channel operation. All registers can be modified during any DMA activity. Any changes made to the DMA registers are reflected immediately in DMA operation.
Table 6. Am186EM Microcontroller Maximum DMA Transfer Rates
Type of Synchronization Selected Unsynchronized Source Synch Destination Synch (CPU needs bus) Destination Synch (CPU does not need bus) Maximum DMA Transfer Rate (Mbyte/s) 40 33 25 20 MHz MHz MHz MHz 10 10 6.6 8 8.25 8.25 5.5 6.6 6.25 6.25 4.16 5 5 5 3.3 4
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Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
20-bit Adder/Subtractor
Adder Control Logic
Timer Request
20 Request Selection Logic DMA Control Logic
DRQ1 DRQ0
Transfer Counter Ch. 1 Destination Address Ch. 1 Source Address Ch. 1 Transfer Counter Ch. 0 Destination Address Ch. 0 Source Address Ch. 0
Interrupt Request
Channel Control Register 1 Channel Control Register 0 20 16
Internal Address/Data Bus
Figure 10.
DMA Unit Block Diagram
DMA Channel Control Registers
Each DMA control register determines the mode of operation for the particular DMA channel. This register specifies the following: n The mode of synchronization n Whether bytes or words are transferred n If an interrupt is generated after the last transfer n If DMA activity ceases after a programmed number of DMA cycles n The relative priority of the DMA channel with respect to the other DMA channel n Whether the source address is incremented, decremented, or maintained constant after each transfer n Whether the source address addresses memory or I/O space n Whether the destination address is incremented, decremented, or maintained constant after transfers n Whether the destination address addresses memory or I/O space
DMA Priority
The DMA channels can be programmed so that one channel is always given priority over the other, or they can be programmed to alternate cycles when both have DMA requests pending. DMA cycles always have priority over internal CPU cycles, except between locked memory accesses or word accesses to odd memory locations. However, an external bus hold takes priority over an internal DMA cycle. Because an interrupt request cannot suspend a DMA operation and the CPU cannot access memory during a DMA cycle, interrupt latency time suffers during sequences of continuous DMA cycles. An NMI request, however, causes all internal DMA activity to halt. This allows the CPU to respond quickly to the NMI request.
Am186/188EM and Am186/188EMLV Microcontrollers
47
PRELIMINARY
ASYNCHRONOUS SERIAL PORT
The Am186EM and AM188EM microcontrollers provide an asynchronous serial port. The asynchronous serial port is a two-pin interface that permits full-duplex bidirectional data transfer. The asynchronous serial port supports the following features: n Full-duplex operation n 7-bit or 8-bit data transfers n Odd, even, or no parity n 1 or 2 stop bits If additional RS-232 signals are required, they can be created with available PIO pins. The asynchronous serial port transmit and receive sections are double buffered. Break character, framing, parity, and overrun error detection are provided. Exception interrupt generation is programmable by the user. The transmit/receive clock is based on the internal processor clock, which is divided down internally to the serial port operating frequency. The serial port permits 7bit and 8-bit data transfers. DMA transfers through the serial port are not supported. The serial port generates one interrupt for any of three serial port events--transmit complete, data received, and error. The serial port can be used in power-save mode, but the software must adjust the transfer rate to correctly reflect the new internal operating frequency and must ensure that the serial port does not receive any information while the frequency is being changed.
SYNCHRONOUS SERIAL INTERFACE
The synchronous serial interface (SSI) lets the Am186EM and AM188EM microcontrollers communicate with application-specific integrated circuits (ASICs) that require reprogrammability but are short on pins. This four-pin interface permits half-duplex, bidirectional data transfer at speeds of up to 20 Mbits/sec. Unlike the asynchronous serial port, the SSI operates in a master/slave configuration. The Am186EM and AM188EM microcontrollers are the master port. The SSI interface provides four pins for communicating with system components: two enables (SDEN0 and SDEN1), a clock (SCLK), and a data pin (SDATA). Five registers are used to control and monitor the interface.
Four-Pin Interface
The two enable pins SDEN1-SDEN0 can be used directly as enables for up to two peripheral devices. Transmit and receive operations are synchronized between the master (Am186EM and AM188EM microcontrollers) and slave (peripheral) by means of the SCLK output. SCLK is derived from the internal processor clock and is the processor clock divided by 2, 4, 8, or 16.
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Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PB=0 DR/DT=0
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=0 DR/DT=0
SDEN SCLK SDATA Poll SSS for PB=0 Write to SSD Write to SSC, bit DE=1 Write to SSD Poll SSS for PB=0 Write to SSD Write to SSC, bit DE=0 Poll SSS for PB=0
Figure 11.
Synchronous Serial Interface Multiple Write
PB=0 DR/DT=0
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=1 DR/DT=0
PB=0 DR/DT=1
PB=0 DR/DT=0
SDEN SCLK SDATA Poll SSS for PB=0 Write to SSD Write to SSC, bit DE=1 Poll SSS for PB=0 Read from SSR (dummy) Read from SSR Poll SSS for PB=0 Write to SSC, bit DE=0 Read from SSR
Figure 12.
Synchronous Serial Interface Multiple Read
Am186/188EM and Am186/188EMLV Microcontrollers
49
PRELIMINARY
PROGRAMMABLE I/O (PIO) PINS
There are 32 pins on the Am186EM and AM188EM microcontrollers that are available as user multipurpose signals. Table 2 and Table 3 on page 30 list the PIO pins. Each of these pins can be used as a user-programmable input or output signal if the normal shared function is not needed. If a pin is enabled to function as a PIO signal, the preassigned signal function is disabled and does not affect the level on the pin. A PIO signal can be configured to operate as an input or output with or without a weak pullup or pulldown, or as an open-drain output. After power-on reset, the PIO pins default to various configurations. The column titled Power-On Reset Status in Table 2 and Table 3 on page 30 lists the defaults for the PIOs. The system initialization code must reconfigure the PIOs as required. The A19-A17 address pins default to normal operation on power-on reset, allowing the processor to correctly begin fetching instructions at the boot address FFFF0h. The DT/R, DEN, and SRDY pins also default to normal operation on power-on reset. Note that emulators use A19, A18, A17, S6, and UZI. If the AD15-AD0 bus override is enabled on power-on reset, then S6/CLKDIV2 and UZI revert to normal operation instead of PIO input with pullup. If BHE/ADEN (186) or RFSH2/ADEN (188) is held Low during power-on reset the AD15-AD0 bus override is enabled.
50
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Storage temperature Am186EM/AM188EM ..................... -65C to +125C Am186EMLV/AM188EMLV............. -65C to +125C Voltage on any pin with respect to ground Am186/188EM ........................... -0.5 V to Vcc +0.5 V Am186/188EMLV ....................... -0.5 V to V cc +0.5 V
the functionality of the device is guaranteed. Am186EM/AM188EM Microcontrollers Commercial (TC) .................................0C to +100C Industrial* (TA)...................................-40C to +85C VCC up to 33 MHz ..................................... 5 V 10% VCC greater than 33 MHz............................ 5 V 5% Am186EMLV/AM188EMLV Microcontrollers Commercial (TA) ................................... 0C to +70C VCC up to 25 MHz ................................. 3.3 V 0.3 V Where: TC = case temperature TA = ambient temperature
Note: Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.
OPERATING RANGES
Operating Ranges define those limits between which
*Industrial versions of Am186EM and AM188EM microcontrollers are available in 20 and 25 MHz operating frequencies only.
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE
Preliminary Symbol VIL VIL1 VIH VIH1 VIH2 Parameter Description Input Low Voltage (Except X1) Clock Input Low Voltage (X1) Input High Voltage (Except RES and X1) Input High Voltage (RES) Clock Input High Voltage (X1) Output Low Voltage Am186EM and AM188EM VOL Am186EMLV and AM188EMLV Output High Voltage(a) Am186EM and AM188EM VOH Am186EMLV and AM188EMLV Power Supply Current @ 0C Am186EM and AM188EM ICC Am186EMLV and AM188EMLV VOL ILI ILO VCLO VCHO Output Low Voltage Input Leakage Current @ 0.5 MHz Output Leakage Current @ 0.5 MHz Clock Output Low Clock Output High VCC = 3.6 V (b) IOL = 2.5 mA (S2-S0) IOL = 2.0 mA (others) 0.45 V VIN VCC 0.45 V VOUT ICLO = 4.0 mA ICHO = -500 A VCC - 0.5 VCC(d) 2.75 0.45 10 10 0.45 IOL = 2.5 mA (S2-S0) IOL = 2.0 mA (others) IOL = 1.5 mA (S2-S0) IOL = 1.0 mA (others) IOH = -2.4 mA @ 2.4 V IOH = -200 A @ VCC -0.5 IOH = -200 A @ VCC -0.5 VCC = 5.5 V (b) 2.4 VCC -0.5 VCC -0.5 Test Conditions Min -0.5 -0.5 2.0 2.4 VCC - 0.8 Max 0.8 0.8 VCC + 0.5 VCC + 0.5 VCC + 0.5 0.45 0.45 Unit V V V V V V V
VCC +0.5 VCC VCC 5.9
V V V mA/ MHz mA/ MHz V A A V V
Notes: a The LCS/ONCE0, MCS3-MCS0, UCS/ONCE1, and RD pins have weak internal pullup resistors. Loading the LCS/ONCE0 and UCS/ONCE1 pins in excess of IOH = -200 A during reset can cause the device to go into ONCE mode. b c d Current is measured with the device in RESET with X1 and X2 driven, and all other non-power pins open but held High or Low. Power supply current for the Am186EMLV and AM188EMLV microcontrollers, which are available in 20 and 25 MHz operating frequencies only. Testing is performed with the pins floating, either during HOLD or by invoking the ONCE mode.
Am186/188EM and Am186/188EMLV Microcontrollers
51
PRELIMINARY
DC CHARACTERISTICS OVER COMMERCIAL OPERATING RANGE (continued)
Preliminary Symbol Parameter Description Test Conditions Nominal Typical Power Supply Current @ 25C VCC = 5.5 V (a) ICC Nominal Am186EMLV and AM188EMLV Typical Power Supply Current @ 25C VCC = 3.6 V (a) (b) ICC Peak ICC Measured Peak ICC Peak ICC Am186EMLV and AM188EMLV Measured Peak ICC VCC = 5.5 V (c) VCC = 3.6 V(b) (c) Typical 4.5 3.0 5.9 4.0 Unit mA/ MHz mA/ MHz mA/ MHz mA/ MHz
a b c
Measured with a device running. Not tested and not guaranteed. Power supply current for the Am186EMLV and AM188EMLV microcontrollers, which are available in 20 and 25 MHz operating frequencies only. Power is measured while device is operating. Not tested and not guaranteed.
Capacitance
Symbol Parameter Description CIN Input Capacitance CIO Output or I/O Capacitance Test Conditions @ 1 MHz @ 1 MHz Preliminary Min Max 10 20 Unit pF pF
Note: Capacitance limits are guaranteed by characterization.
52
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Power Supply Current
For the typical system specification shown in Figure 13, ICC has been measured at 3.0 mA per MHz of system clock. For the typical system specification shown in Figure 14, ICC has been measured at 4.5 mA per MHz of system clock. The typical system is measured while the system is executing code in a typical application with maximum voltage and at room temperature. Actual power supply current is dependent on system design and may be greater or less than the typical ICC figure presented here. Typical current in Figure 13 is given by: ................. ICC = 3.0 mA freq(MHz). Typical current in Figure 14 is given by: ................. ICC = 4.5 mA freq(MHz). Please note that dynamic ICC measurements are dependent upon chip activity, operating frequency, output buffer logic, and capacitive/resistive loading of the outputs. For these ICC measurements, the devices were set to the following modes: n No DC loads on the output buffers n Output capacitive load set to 35 pF n AD bus set to data only n PIOs are disabled n Timer, serial port, refresh, and DMA are enabled
Table 7 shows the variables that are used to calculate the typical power consumption value for each version of the Am186EMLV and AM188EMLV microcontrollers. Table 7. Typical Power Consumption Calculation for the Am186EMLV and AM188EMLV
MHz ICC Volts / 1000 = P MHz Typical ICC Volts 16 3.0 3.6 20 3.0 3.6 25 3.0 3.6 Typical Power in Watts 0.173 0.216 0.270
140 120 100 80
ICC (mA)
60 40 20 0 10
25 MHz 20 MHz 16 MHz
20
30
Clock Frequency (MHz)
Figure 13. Typical ICC Versus Frequency for the Am186EMLV and AM188EMLV
280 240 200 40 MHz 160 120 80 40 0 10 20 30 40 20 MHz 25 MHz 33 MHz
ICC (mA)
Clock Frequency (MHz)
Figure 14.
Typical ICC Versus Frequency for the Am186EM and AM188EM
Am186/188EM and Am186/188EMLV Microcontrollers
53
PRELIMINARY
THERMAL CHARACTERISTICS TQFP Package
The Am186EM and AM188EM microcontrollers are specified for operation with case temperature ranges from 0C to +100C for a commercial temperature device. Case temperature is measured at the top center of the package as shown in Figure 15. The various temperatures and thermal resistances can be determined using the equations in Figure 16 with information given in Table 8. JA is the sum of JC and CA. JC is the internal thermal resistance of the assembly. CA is the case to ambient thermal resistance.
The variable P is power in watts. Typical power supply current (ICC) for the Am186EM and AM188EM microcontrollers is 5.9 mA per MHz of clock frequency. JA TC JC CA
JA = JC + CA Figure 15. Thermal Resistance(C/Watt)
JA = JC + CA P=5.9 mA freq (MHz) VCC TJ =TC +( PJC ) TJ =TA + (PJA ) TC =TJ -( PJC ) TC =TA +( PCA ) TA =TJ -( PJA ) TA =TC -( PCA ) Figure 16. Thermal Characteristics Equations
Table 8.
Thermal Characteristics (C/Watt)
Airflow (Linear Feet per Minute) 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm 0 fpm 200 fpm 400 fpm 600 fpm JC 7 7 7 7 10 10 10 10 5 5 5 5 6 6 6 6 CA 38 32 28 26 46 36 30 28 18 16 14 12 24 22 20 18 JA 45 39 35 33 56 46 40 38 23 21 19 17 30 28 26 24
Package/Board
PQFP/2-Layer
TQFP/2-Layer
PQFP/4-Layer to 6-Layer
TQFP/4-Layer to 6-Layer
54
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Typical Ambient Temperatures
The typical ambient temperature specifications are based on the following assumptions and calculations: The commercial operating range of the Am186EM and AM188EM microcontrollers is a case temperature TC of 0 to 100 degrees Centigrade. TC is measured at the top center of the package. An increase in the ambient temperature causes a proportional increase in TC. The 40-MHz microcontroller is specified as 5.0 V, plus or minus 5%. Therefore, 5.25 V is used for calculating typical power consumption on the 40-MHz microcontroller. Microcontrollers up to 33 MHz are specified as 5.0 V, plus or minus 10%. Therefore, 5.5 V is used for calculating typical power consumption up to 33 MHz. Typical power supply current (ICC) in normal usage is estimated at 5.9 mA per MHz of microcontroller clock rate. Typical power consumption (watts) = (5.9 mA/MHz) times microcontroller clock rate times voltage divided by 1000. Table 9 shows the variables that are used to calculate the typical power consumption value for each version of the Am186EM and AM188EM microcontrollers.
Table 10. Junction Temperature Calculation
Speed/ Pkg/ Board 40/P2 40/T2 40/P4-6 40/T4-6 33/P2 33/T2 33/P4-6 33/T4-6 25/P2 25/T2 25/P4-6 25/T4-6 20/P2 20/T2 20/P4-6 20/T4-6 TJ = TC + ( P JC ) TC 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 P 1.239 1.239 1.239 1.239 1.07085 1.07085 1.07085 1.07085 0.81125 0.81125 0.81125 0.81125 0.649 0.649 0.649 0.649
JC
7 10 5 6 7 10 5 6 7 10 5 6 7 10 5 6
TJ 108.7 112.4 106.2 107.4 107.5 110.7 105.3 106.4 105.7 108.1 104.1 104.9 104.5 106.5 103.2 103.9
Table 9. Typical Power Consumption Calculation
P = MHz ICC Volts / 1000 MHz 40 33 25 20 Typical ICC 5.9 5.9 5.9 5.9 Volts 5.25 5.5 5.5 5.5 Typical Power (P) in Watts 1.239 1.07085 0.81125 0.649
By using TJ from Table 10, the typical power consumption value from Table 9, and a JA value from Table 8, the typical ambient temperature TA can be calculated using the following formula from Figure 16. TA = TJ - ( P JA ) For example, TA for a 40-MHz PQFP design with a 2layer board and 0 fpm airflow is calculated as follows: TA = 108.673 - ( 1.239 45 ) TA = 52.918 In this calculation, TJ comes from Table 10, P comes from Table 9, and JA comes from Table 8. See Table 11. TA for a 33-MHz TQFP design with a 4-layer to 6-layer board and 200 fpm airflow is calculated as follows: TA = 106.4251 - ( 1.07085 28 ) TA = 76.4413 See Table 14 for the result of this calculation. Table 11 through Table 14 and Figure 17 through Figure 20 show TA based on the preceding assumptions and calculations for a range of JA values with airflow from 0 linear feet per minute to 600 linear feet per minute.
Thermal resistance is a measure of the ability of a package to remove heat from a semiconductor device. A safe operating range for the device can be calculated using the following formulas from Figure 16 and the variables in Table 8. By using the maximum case rating T C , the typical power consumption value from Table 9, and JC from Table 8, the junction temperature TJ can be calculated by using the following formula from Figure 16. TJ = TC + ( P JC ) Table 10 shows TJ values for the various versions of the Am186EM and AM188EM microcontrollers. The column titled Speed/Pkg/Board in Table 10 indicates the clock speed in MHz, the type of package (P for PQFP and T for TQFP), and the type of board (2 for 2-layer and 4-6 for 4layer to 6-layer).
Am186/188EM and Am186/188EMLV Microcontrollers
55
PRELIMINARY Table 11 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a 2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 17 illustrates the typical temperatures in Table 11.
Table 11. Typical Ambient Temperatures for PQFP with 2-Layer Board
Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 52.918 59.3077 69.1725 75.338 Linear Feet per Minute Airflow 200 fpm 400 fpm 60.352 65.308 65.7328 70.0162 74.04 77.285 79.232 81.828 600 fpm 67.786 72.1579 78.9075 83.126
90
Typical Ambient Temperature (Degrees C)
s 80 s 70 s x x
s x
I
x
I
q
I
60 q
q
I
q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
50
40
0 fpm 200 fpm 400 fpm 600 fpm
Airflow (Linear Feet Per Minute)
Figure 17.
Typical Ambient Temperatures for PQFP with 2-Layer Board
56
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY Table 12 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a 2-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 18 illustrates the typical temperatures in Table 12.
Table 12.
Typical Ambient Temperatures for TQFP with 2-Layer Board
Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 43.006 50.7409 62.6825 70.146 Linear Feet per Minute Airflow 200 fpm 400 fpm 55.396 62.83 61.4494 67.8745 70.795 75.6625 76.636 80.53 600 fpm 65.308 70.0162 77.285 81.828
Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz
90 Typical Ambient Temperature (Degrees C)
s 80 s s x x
70
s
x
I I
q
x 60
I
q
q
I
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz 40
0 fpm 200 fpm 400 fpm 600 fpm
50
q
Airflow (Linear Feet Per Minute)
Figure 18.
Typical Ambient Temperatures for TQFP with 2-Layer Board
Am186/188EM and Am186/188EMLV Microcontrollers
57
PRELIMINARY Table 13 shows typical maximum ambient temperatures in degrees Centigrade for a PQFP package used with a 4-layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 19 illustrates the typical temperatures in Table 13.
Table 13. Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board
Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 77.698 80.7247 85.3975 88.318 Linear Feet per Minute Airflow 200 fpm 400 fpm 80.176 82.654 82.8664 85.0081 87.02 88.6425 89.616 90.914 600 fpm 85.132 87.1498 90.265 92.212
95 s Typical Ambient Temperature (Degrees C) s 90 s x 85 x s x x
I I
q
I I
80 q q
q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
75
70
0 fpm 200 fpm 400 fpm 600 fpm
Airflow (Linear Feet Per Minute)
Figure 19.
Typical Ambient Temperatures for PQFP with 4-Layer to 6-Layer Board
58
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY Table 14 shows typical maximum ambient temperatures in degrees Centigrade for a TQFP package used with a 4-layer to 6-layer board. The typical ambient temperatures are based on a 100-degree Centigrade maximum case temperature. Figure 20 illustrates the typical temperatures in Table 14.
Table 14. Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board
Microcontroller Speed 40 MHz 33 MHz 25 MHz 20 MHz Typical Power (Watts) 1.239 1.07085 0.81125 0.649 0 fpm 70.264 74.2996 80.53 84.424 Linear Feet per Minute Airflow 200 fpm 400 fpm 72.742 75.22 76.4413 78.583 82.1525 83.775 85.722 87.02 600 fpm 77.698 80.7247 85.3975 88.318
95
Typical Ambient Temperature (Degrees C)
90 s s s 85 s x x 80 x x
I I I
q q
Legend: q 40 MHz H 33 MHz x 25 Mhz s 20 MHz
75
I
q 70 q
0 fpm 200 fpm 400 fpm 600 fpm
Airflow (Linear Feet Per Minute)
Figure 20.
Typical Ambient Temperatures for TQFP with 4-Layer to 6-Layer Board
Am186/188EM and Am186/188EMLV Microcontrollers
59
PRELIMINARY
COMMERCIAL SWITCHING CHARACTERISTICS AND WAVEFORMS
In the switching waveforms that follow, several abbreviations are used to indicate the specific periods of a bus cycle. These periods are referred to as time states. A typical bus cycle is composed of four consecutive time states: t1, t2, t3, and t4. Wait states, which represent multiple t3 states, are referred to as tw states. When no bus cycle is pending, an idle (ti) state occurs. In the switching parameter descriptions, the multiplexed address is referred to as the AD address bus; the demultiplexed address is referred to as the A address bus.
Key to Switching Waveforms
WAVEFORM INPUT Must be Steady May Change from H to L May Change from L to H Don't Care, Any Change Permitted Does Not Apply OUTPUT Will be Steady Will be Changing from H to L Will be Changing from L to H Changing, State Unknown Center Line is HighImpedance Off State Invalid
Invalid
60
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Alphabetical Key to Switching Parameter Symbols
Parameter Symbol tARYCH tARYCHL tARYLCL tAVBL tAVCH tAVLL tAVRL tAVWL tAZRL tCH1CH2 tCHAV tCHCK tCHCL tCHCSV tCHCSX tCHCTV tCHCV tCHCZ tCHDX tCHLH tCHLL tCHRFD tCHSV tCICOA tCICOB tCKHL tCKIN tCKLH tCL2CL1 tCLARX tCLAV tCLAX tCLAZ tCLCH tCLCK tCLCL tCLCLX tCLCSL tCLCSV tCLDOX tCLDV No. 49 51 52 87 14 12 66 65 24 45 68 38 44 67 18 22 64 63 8 9 11 79 3 69 70 39 36 40 46 50 5 6 15 43 37 42 80 81 16 30 7 Description ARDY Resolution Transition Setup Time ARDY Inactive Holding Time ARDY Setup Time A Address Valid to WHB, WLB Low AD Address Valid to Clock High AD Address Valid to ALE Low A Address Valid to RD Low A Address Valid to WR Low AD Address Float to RD Active CLKOUTA Rise Time CLKOUTA High to A Address Valid X1 High Time CLKOUTA High Time CLKOUTA High to LCS/UCS Valid MCS/PCS Inactive Delay Control Active Delay 2 Command Lines Valid Delay (after Float) Command Lines Float Delay Status Hold Time ALE Active Delay ALE Inactive Delay CLKOUTA High to RFSH valid Status Active Delay X1 to CLKOUTA Skew X1 to CLKOUTB Skew X1 Fall Time X1 Period X1 Rise Time CLKOUTA Fall Time ARDY Active Hold Time AD Address Valid Delay Address Hold AD Address Float Delay CLKOUTA Low Time X1 Low Time CLKOUTA Period LCS Inactive Delay LCS Active Delay MCS/PCS Active Delay Data Hold Time Data Valid Delay Parameter Symbol tCLDX tCLEV tCLHAV tCLRF tCLRH tCLRL tCLSH tCLSL tCLSRY tCLTMV tCOAOB tCVCTV tCVCTX tCVDEX tCXCSX tDVCL tDVSH tDXDL tHVCL tINVCH tINVCL tLCRF tLHAV tLHLL tLLAX tLOCK tLRLL tRESIN tRFCY tRHAV tRHDX tRHLH tRLRH tSHDX tSLDV tSRYCL tWHDEX tWHDX tWHLH tWLWH No. 2 71 62 82 27 25 4 72 48 55 83 20 31 21 17 1 75 19 58 53 54 86 23 10 13 61 84 57 85 29 59 28 26 77 78 47 35 34 33 32 Data in Hold CLKOUTA Low to SDEN Valid HLDA Valid Delay CLKOUTA High to RFSH Invalid RD Inactive Delay RD Active Delay Status Inactive Delay CLKOUTA Low to SCLK Low SRDY Transition Hold Time Timer Output Delay CLKOUTA to CLKOUTB Skew Control Active Delay 1 Control Inactive Delay DEN Inactive Delay MCS/PCS Hold from Command Inactive Data in Setup Data Valid to SCLK High DEN Inactive to DT/R Low HOLD Setup Peripheral Setup Time DRQ Setup Time LCS Inactive to RFSH Active Delay ALE High to Address Valid ALE Width AD Address Hold from ALE Inactive Maximum PLL Lock Time LCS Precharge Pulse Width RES Setup Time RFSH Cycle Time RD Inactive to AD Address Active RD High to Data Hold on AD Bus RD Inactive to ALE High RD Pulse Width SCLK High to SPI Data Hold SCLK Low to SPI Data Valid SRDY Transition Setup Time WR Inactive to DEN Inactive Data Hold after WR WR Inactive to ALE High WR Pulse Width Description
Note: The following parameters are not defined or used as this time: 41, 56, 60, 73, 74, 76.
Am186/188EM and Am186/188EMLV Microcontrollers
61
PRELIMINARY
Numerical Key to Switching Parameter Symbols
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 42 Parameter Symbol tDVCL tCLDX tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLAZ tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCVDEX tCHCTV tLHAV tAZRL tCLRL tRLRH tCLRH tRHLH tRHAV tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tCKIN tCLCK tCHCK tCKHL tCKLH tCLCL Description Data in Setup Data in Hold Status Active Delay Status Inactive Delay AD Address Valid Delay Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low AD Address Hold from ALE Inactive AD Address Valid to Clock High AD Address Float Delay MCS/PCS Active Delay MCS/PCS Hold from Command Inactive MCS/PCS Inactive Delay DEN Inactive to DT/R Low Control Active Delay 1 DEN Inactive Delay Control Active Delay 2 ALE High to Address Valid AD Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High RD Inactive to AD address Active Data Hold Time Control Inactive Delay WR Pulse Width WR Inactive to ALE High Data Hold after WR WR Inactive to DEN Inactive X1 Period X1 Low Time X1 High Time X1 Fall Time X1 Rise Time CLKOUTA Period Number 43 44 45 46 47 48 49 50 51 52 53 54 55 57 58 59 61 62 63 64 65 66 67 68 69 70 71 72 75 77 78 79 80 81 82 83 84 85 86 87 Parameter Symbol tCLCH tCHCL tCH1CH2 tCL2CL1 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV tRESIN tHVCL tRHDX tLOCK tCLHAV tCHCZ tCHCV tAVWL tAVRL tCHCSV tCHAV tCICOA tCICOB tCLEV tCLSL tDVSH tSHDX tSLDV tCHRFD tCLCLX tCLCSL tCLRF tCOAOB tLRLL tRFCY tLCRF tAVBL Description CLKOUTA Low Time CLKOUTA High Time CLKOUTA Rise Time CLKOUTA Fall Time SRDY Transition Setup Time SRDY Transition Hold Time ARDY Resolution Transition Setup Time ARDY Active Hold Time ARDY Inactive Holding Time ARDY Setup Time Peripheral Setup Time DRQ Setup Time Timer Output Delay RES Setup Time HOLD Setup RD High to Data Hold on AD Bus Maximum PLL Lock Time HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float) A Address Valid to WR Low A Address Valid to RD Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to Address Valid X1 to CLKOUTA Skew X1 to CLKOUTB Skew CLKOUTA Low to SDEN Valid CLKOUTA Low to SCLK Low Data Valid to SCLK High SCLK High to SPI Data Hold SCLK Low to SPI Data Valid CLKOUTA High to RFSH Valid LCS Inactive Delay LCS Active Delay CLKOUTA High to RFSH Invalid CLKOUTA to CLKOUTB Skew LCS Precharge Pulse Width RFSH Cycle Time LCS Inactive to RFSH Active Delay A Address Valid to WHB, WLB Low
Note: The following parameters are not defined or used at this time: 41, 56, 60, 73, 74, and 76.
62
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Read Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold(c) General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV AD Address Valid Delay and BHE 6 tCLAX Address Hold 8 tCHDX Status Hold Time 9 tCHLH ALE Active Delay 10 11 12 tLHLL tCHLL tAVLL ALE Width Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 0 0 0 0 0 25 25 25 25 25 tCLCL -10=40 25 tCLCH -2 tCHCL -2 0 tCLAX =0 0 tCLCH -2 0 0 0 0 0 20 0 0 2tCLCL -15=85 25 25 25 25 25 25 25 tCLCH -2 tCHCL -2 0 tCLAX =0 0 tCLCH -2 0 0 0 0 0 15 0 0 2tCLCL -15= 65 0 tCLCH -3 tCLCL -10= 30 0 2tCLCL -15= 65 0 0 20 20 20 20 20 20 tCLCL -10= 30 20 10 3 0 0 0 0 0 20 20 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE 13 tLLAX Inactive(a) 14 tAVCH AD Address Valid to Clock High 15 tCLAZ AD Address Float Delay 16 tCLCSV MCS/PCS Active Delay MCS/PCS Hold from Command 17 tCXCSX Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 19 tDXDL DEN Inactive to DT/R Low(a) 20 tCVCTV Control Active Delay 1(b) 21 tCVDEX DEN Inactive Delay 22 tCHCTV Control Active Delay 2(b) 23 tLHAV ALE High to Address Valid Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 25 tCLRL RD Active Delay 26 27 28 29 59 66 67 68 tRLRH tCLRH tRHLH tRHAV tRHDX tAVRL tCHCSV tCHAV RD Pulse Width
25
20
RD Inactive Delay 0 (a) RD Inactive to ALE High tCLCH -3 RD Inactive to AD Address tCLCL -10=40 Active(a) RD High to Data Hold on AD Bus(c) 0 A Address Valid to RD Low(a) CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid 2tCLCL -15=85 0 0
20
ns ns ns ns ns
25 25
20 20
ns ns
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the DEN, INTA1-INTA0, WR, WHB, and WLB signals. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186/188EM and Am186/188EMLV Microcontrollers
63
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Read Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Requirements 1 tDVCL Data in Setup 2 tCLDX Data in Hold(c) General Timing Responses 3 tCHSV Status Active Delay 4 tCLSH Status Inactive Delay 5 tCLAV AD Address Valid Delay and BHE 6 tCLAX Address Hold 7 tCLDV Data Valid Delay 8 tCHDX Status Hold Time 9 tCHLH ALE Active Delay 10 11 12 tLHLL tCHLL tAVLL ALE Width Preliminary 33 MHz 40 MHz Min Max Min Max 8 3 0 0 0 0 0 0 15 15 15 25 15 15 tCLCL -10=20 15 tCLCH -2 tCHCL -2 15 15 0 tCLAX =0 0 tCLCH -2 15 15 15 15 0 0 0 0 0 7.5 0 0 2tCLCL -10=40 0 tCLCH -2 tCLCL -5 =20 0 2tCLCL -10=40 0 0 12 12 12 12 12 12 tCLCL -5 =20 12 5 2 0 0 0 0 0 0 12 12 12 20 12 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
ALE Inactive Delay AD Address Valid to ALE Low(a) tCLCH -2 AD Address Hold from ALE 13 tLLAX tCHCL-2 Inactive(a) 14 tAVCH AD Address Valid to Clock High 0 15 tCLAZ AD Address Float Delay tCLAX =0 16 tCLCSV MCS/PCS Active Delay 0 MCS/PCS Hold from Command 17 tCXCSX tCLCH -2 Inactive(a) 18 tCHCSX MCS/PCS Inactive Delay 0 (a) 19 tDXDL DEN Inactive to DT/R Low 0 20 tCVCTV Control Active Delay 1(b) 0 21 tCVDEX DEN Inactive Delay 0 22 tCHCTV Control Active Delay 2(b) 0 23 tLHAV ALE High to Address Valid 10 Read Cycle Timing Responses 24 tAZRL AD Address Float to RD Active 0 25 tCLRL RD Active Delay 0 26 tRLRH RD Pulse Width 2tCLCL -15=45 27 tCLRH RD Inactive Delay 0 28 tRHLH RD Inactive to ALE High(a) tCLCH -3 RD Inactive to AD Address 29 tRHAV tCLCL -10=20 Active(a) 59 tRHDX RD High to Data Hold on AD Bus(c) 0 (a) 66 tAVRL A Address Valid to RD Low 2tCLCL -15=45 67 tCHCSV CLKOUTA High to LCS/UCS Valid 0 68 tCHAV CLKOUTA High to A Address Valid 0
15 15
10 12
15 15
10 10
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the DEN, INTA1-INTA0, WR, WHB, and WLB signals. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
64
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Read Cycle Waveforms
t1 t2 t3 tW CLKOUTA
66
t4
A19-A0
68
Address
8
S6
S6
14 6 1
S6
AD15-AD0*, AD7-AD0**
Address
Data
2
AO15-AO8**
23 9 11 15 10 24
Address
29 59 28 26 25 27
ALE
RD
5
12
BHE*
67 13
BHE
18
LCS, UCS MCS1-MCS0, PCS6-PCS5, PCS3-PCS0 DEN
19 16 17
20
21
DT/R *** 22 S2-S0
3 4
*** 22
Status
UZI
Notes:
* **
Am186EM microcontroller only AM188EM microcontroller only Changes in t4 phase of the clock preceding next bus cycle if followed by read, INTA, or halt
***
Am186/188EM and Am186/188EMLV Microcontrollers
65
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Write Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Responses 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 22 23 30 31 32 33 34 35 65 67 68 87 tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCHCTV tLHAV tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tAVWL tCHCSV tCHAV tAVBL Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) AD Address Valid to Clock High MCS/PCS Active Delay MCS/PCS Hold from Command Inactive(a) MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) Control Active Delay 2 ALE High to Address Valid Data Hold Time Control Inactive Delay(b) tCLCH tCHCL 0 0 tCLCH 0 0 0 0 20 0 0 2tCLCL -10 =90 tCLCH -2 tCLCL -10= 40 tCLCH -3 tCLCL +tCHCL -3 0 0 tCHCL -3 25 25 25 25 25 25 25 25 tCLCL -10= 40 25 tCLCH tCHCL 0 0 tCLCH 0 0 0 0 15 0 0 2tCLCL -10 =70 tCLCH -2 tCLCL -10= 30 tCLCH -3 tCLCL +tCHCL -3 0 0 tCHCL -3 20 20 20 20 20 20 20 20 Preliminary 20 MHz 25 MHz Min Max Min Max 0 0 0 0 0 0 25 tCLCL -10= 30 20 25 25 25 25 25 0 0 0 0 0 0 20 20 20 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle Timing Responses
WR Pulse Width WR Inactive to ALE High(a) Data Hold after WR(a)
WR Inactive to DEN Inactive(a) A Address Valid to WR Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. This parameter applies to the DEN, INTA1-INTA0, WR, WHB, and WLB signals.
66
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Write Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Responses 3 4 5 6 7 8 9 10 11 12 13 14 16 17 18 19 20 22 23 30 31 32 33 34 35 65 67 68 87 tCHSV tCLSH tCLAV tCLAX tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tLLAX tAVCH tCLCSV tCXCSX tCHCSX tDXDL tCVCTV tCHCTV tLHAV tCLDOX tCVCTX tWLWH tWHLH tWHDX tWHDEX tAVWL tCHCSV tCHAV tAVBL Status Active Delay Status Inactive Delay AD Address Valid Delay and BHE Address Hold Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Valid to ALE Low(a) AD Address Hold from ALE Inactive(a) AD Address Valid to Clock High MCS/PCS Active Delay MCS/PCS Hold from Command Inactive(a) MCS/PCS Inactive Delay DEN Inactive to DT/R Low(a) Control Active Delay 1(b) Control Active Delay 2 ALE High to Address Valid Data Hold Time Control Inactive Delay(b) tCLCH tCHCL 0 0 tCLCH 0 0 0 0 10 0 0 2tCLCL -10 =50 tCLCH -2 tCLCL -10= 20 tCLCH -5 tCLCL +tCHCL -3 0 0 tCHCL -3 15 15 15 15 15 15 15 15 tCLCL -10= 20 15 tCLCH tCHCL 0 0 tCLCH 0 0 0 0 7.5 0 0 2tCLCL -10 =40 tCLCH -2 tCLCL -10= 15 tCLCH tCLCL +tCHCL -1.25 0 0 tCHCL -1.25 10 10 12 12 12 12 12 12 Preliminary 33 MHz 40 MHz Min Max Min Max 0 0 0 0 0 0 15 tCLCL -5 =20 12 15 15 15 25 15 0 0 0 0 0 0 12 12 12 12 20 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Write Cycle Timing Responses
WR Pulse Width WR Inactive to ALE High(a) Data Hold after WR(a)
WR Inactive to DEN Inactive(a) A Address Valid to WR Low CLKOUTA High to LCS/UCS Valid CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. This parameter applies to the DEN, INTA1-INTA0, WR, WHB, and WLB signals.
Am186/188EM and Am186/188EMLV Microcontrollers
67
PRELIMINARY
Write Cycle Waveforms
t1 t2 t3 tW CLKOUTA
65
t4
A19-A0
68
Address
8
S6
S6
14 7
S6
30
AD15-AD0*, AD7-AD0** AO15-AO8**
23 9
Address
6
Data
Address
11 13 10 32 31 33 12 20 20 87 5 31 34
ALE
WR
WHB*, WLB* WB** BHE*
67
BHE
LCS, UCS
16 18 17 20 35 31
MCS3-MCS0, PCS6-PCS5, PCS3-PCS0 DEN
19
DT/R
22
*** Status
22
***
S2-S0
3
4
UZI
Note:
* **
Am186EM microcontroller only AM188EM microcontroller only Changes in t4 phase of the clock preceding next bus cycle if followed by read, INTA, or halt.
***
68
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Read Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Requirements 1 2 5 7 8 9 10 11 23 80 81 84 tDVCL tCLDX tCLAV tCLDV tCHDX tCHLH tLHLL tCHLL tLHAV tCLCLX tCLCSL tLRLL tAZRL tCLRL tRLRH tCLRH tRHLH tRHDX tAVRL tCHAV Data in Setup Data in Hold(b) AD Address Valid Delay and BHE Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay ALE High to Address Valid LCS Inactive Delay LCS Active Delay LCS Precharge Pulse Width 20 0 0 tCLCL + tCLCH -3 0 0 2tCLCL -15 =85 0 tCLCH -3 Bus(b) 0 2tCLCL -15 =85 0 25 25 25 25 25 tCLCL -10= 40 25 15 0 0 tCLCL + tCLCH -3 0 0 2tCLCL -15 =65 0 tCLCH -3 0 2tCLCL -15 =65 0 20 20 20 20 20 Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 0 0 0 25 tCLCL -10= 30 20 25 25 10 3 0 0 0 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses
Read Cycle Timing Responses 24 25 26 27 28 59 66 68 AD Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High(a) RD High to Data Hold on AD A Address Valid to RD Low CLKOUTA High to A Address Valid ns ns ns ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
Am186/188EM and Am186/188EMLV Microcontrollers
69
PRELIMINARY
SWITCHING CHARACTERISTICS over Commercial operating range PSRAM Read Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Requirements 1 2 5 7 8 9 10 11 23 80 81 84 tDVCL tCLDX tCLAV tCLDV tCHDX tCHLH tLHLL tCHLL tLHAV tCLCLX tCLCSL tLRLL tAZRL tCLRL tRLRH tCLRH tRHLH tRHDX tAVRL tCHAV Data in Setup Data in Hold(b) AD Address Valid Delay and BHE Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay ALE High to Address Valid LCS Inactive Delay LCS Active Delay LCS Precharge Pulse Width 10 0 0 tCLCL + tCLCH -3 0 0 2tCLCL -15 =45 0 tCLCH -3 Bus(b) 0 2tCLCL -15 =45 0 15 15 15 15 15 tCLCL -10= 20 15 7.5 0 0 tCLCL + tCLCH -1.25 0 0 2tCLCL -10 =40 0 tCLCH -1.25 0 2tCLCL -10 =40 0 10 12 10 12 12 Preliminary 33 MHz 40 MHz Min Max Min Max 8 3 0 0 0 15 tCLCL -5= 20 12 15 15 5 2 0 0 0 12 12 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses
Read Cycle Timing Responses 24 25 26 27 28 59 66 68 AD Address Float to RD Active RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE High(a) RD High to Data Hold on AD A Address Valid to RD Low CLKOUTA High to A Address Valid ns ns ns ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. If either spec 2 or spec 59 is met with respect to data hold time, the part will function correctly.
70
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PSRAM Read Cycle Waveforms
t1 t2
t3 t4
t1
tW CLKOUTA
66
A19-A0
68
Address
8
S6 AD15-AD0*, AD7-AD0**
S6
7 1
S6
Address
Data
2
Address
AO15-AO8**
23 9 11
Address
59
ALE
10 24 26 27 5 25 27 28
RD
LCS
80 84 81 80
Notes:
* **
Am186EM microcontroller only AM188EM microcontroller only
Am186/188EM and Am186/188EMLV Microcontrollers
71
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Write Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Responses AD Address Valid Delay and 5 tCLAV BHE 7 8 9 10 11 23 20 80 81 84 tCLDV tCHDX tCHLH tLHLL tCHLL tLHAV tCVCTV tCLCLX tCLCSL tLRLL Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay ALE High to Address Valid Control Active Delay 1(b) LCS Inactive Delay LCS Active Delay LCS Precharge Pulse Width 20 0 0 0 tCLCL + tCLCH -3 0 Delay(b) 0 2tCLCL-10 =90 tCLCH -2 tCLCL -10=40 tCLCL +tCHCL -3 0 tCHCL -3 25 25 25 25 25 25 tCLCL -10=40 25 15 0 0 0 tCLCL + tCLCH - 3 0 0 2tCLCL -10 =70 tCLCH -2 tCLCL -10=30 tCLCL +tCHCL -3 0 tCHCL -3 20 20 20 ns ns ns ns ns ns ns ns 20 20 20 Preliminary 20 MHz 25 MHz Min Max Min Max
Unit
0 0 0
25 25 25
0 0 0
20 20 20
ns ns ns ns ns ns ns ns ns ns
tCLCL -10=30 20
Write Cycle Timing Responses 30 31 32 33 34 65 68 87 tCLDOX tCVCTX tWLWH tWHLH tWHDX tAVWL tCHAV tAVBL Data Hold Time Control Inactive
WR Pulse Width WR Inactive to ALE High(a) Data Hold after WR(a)
A Address Valid to WR Low CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. This parameter applies to the DEN, WR, WHB, and WLB signals.
72
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Write Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Responses AD Address Valid Delay and 5 tCLAV BHE 7 8 9 10 11 20 23 80 81 84 tCLDV tCHDX tCHLH tLHLL tCHLL tCVCTV tLHAV tCLCLX tCLCSL tLRLL Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay Control Active Delay 1 LCS Inactive Delay LCS Active Delay LCS Precharge Pulse Width
(b)
Preliminary 33 MHz 40 MHz Min Max Min Max
Unit
0 0 0
15 15 15
0 0 0
12 12 12
ns ns ns ns ns ns ns ns ns ns
tCLCL -10=20 15 0 10 0 0 tCLCL + tCLCH -3 0 Delay(b) 0 2tCLCL -10 =50 tCLCH -2 tCLCL -10=20 tCLCL +tCHCL -3 0 tCHCL -3 15 15 15 15 15 15
tCLCL -5=20 12 0 7.5 0 0 tCLCL + tCLCH -1.25 0 0 2tCLCL -10 =40 tCLCH -2 tCLCL -10=15 tCLCL +tCHCL -1.25 0 tCHCL -1.25 10 12 12 12 12 12
ALE High to Address Valid
Write Cycle Timing Responses 30 31 32 33 34 65 68 87 tCLDOX tCVCTX tWLWH tWHLH tWHDX tAVWL tCHAV tAVBL Data Hold Time Control Inactive ns ns ns ns ns ns ns ns
WR Pulse Width WR Inactive to ALE High(a) Data Hold after WR(a)
A Address Valid to WR Low CLKOUTA High to A Address Valid A Address Valid to WHB, WLB Low
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. This parameter applies to the DEN, WR, WHB, and WLB signals.
Am186/188EM and Am186/188EMLV Microcontrollers
73
PRELIMINARY
PSRAM Write Cycle Waveforms
t1 t2 t3 tW CLKOUTA
65
t4
t1
A19-A0
68
Address
8
S6
S6
7
S6
30
AD15-AD0*, AD7-AD0**
Address
Data
AO15-AO8**
23 9 11
Address
34
ALE
10 32
33
WR
31
5 20
20
31
WHB*, WLB* WB** LCS
87
80 84
81
80
Notes:
* **
Am186EM microcontroller only AM188EM microcontroller only
74
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Refresh Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Responses 9 10 11 25 26 27 28 80 81 79 82 85 86 tCHLH tLHLL tCHLL tCLRL tRLRH tCLRH tRHLH tCLCLX tCLCSL tCLRFD tCLRF tRFCY tLCRF ALE Active Delay ALE Width ALE Inactive Delay RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE LCS Inactive Delay LCS Active Delay CLKOUTA Low to RFSH Valid CLKOUTA High to RFSH Invalid RFSH Cycle Time LCS Inactive to RFSH Active Delay High(a) 0 2tCLCL -15 =85 0 tCLCH -3 0 0 0 0 6 * tCLCL 2tCLCL -3 25 25 25 25 25 tCLCL -10= 40 25 25 0 2tCLCL -15 =65 0 tCLCH -3 0 0 0 0 6 * tCLCL 2tCLCL -3 20 20 20 20 20 Preliminary 20 MHz 25 MHz Min Max Min Max 25 tCLCL -10= 30 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Read/Write Cycle Timing Responses
Refresh Timing Cycle Parameters
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a Equal loading on referenced pins.
Am186/188EM and Am186/188EMLV Microcontrollers
75
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range PSRAM Refresh Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Responses 9 10 11 25 26 27 28 80 81 79 82 85 86 tCHLH tLHLL tCHLL tCLRL tRLRH tCLRH tRHLH tCLCLX tCLCSL tCLRFD tCLRF tRFCY tLCRF ALE Active Delay ALE Width ALE Inactive Delay RD Active Delay RD Pulse Width RD Inactive Delay RD Inactive to ALE LCS Inactive Delay LCS Active Delay CLKOUTA Low to RFSH Valid CLKOUTA High to RFSH Invalid RFSH Cycle Time LCS Inactive to RFSH Active Delay High(a) 0 2tCLCL -15 =45 0 tCLCH -3 0 0 0 0 6 * tCLCL 2tCLCL -3 15 15 15 15 15 tCLCL -10=20 15 15 0 2tCLCL -10 =40 0 tCLCH -2 0 0 0 0 6 * tCLCL 2tCLCL -1.25 12 12 12 12 12 Preliminary 33 MHz 40 MHz Min Max Min Max 15 tCLCL -5 =20 12 10 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns
Read/Write Cycle Timing Responses
Refresh Timing Cycle Parameters
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a Equal loading on referenced pins.
76
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PSRAM Refresh Cycle Waveforms
t1 t2 t3 tW * CLKOUTA t4 t1
A19-A0
9 11
Address
ALE
27 10 26 80 25 27 81 28
RD
LCS
79
RFSH
82
85 86
Note: * The period tw is fixed at 3 wait states for PSRAM auto refresh only.
Am186/188EM and Am186/188EMLV Microcontrollers
77
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Interrupt Acknowledge Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Requirements 1 2 3 4 7 8 9 10 11 12 15 19 20 21 22 23 31 68 tDVCL tCLDX tCHSV tCLSH tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tCLAZ tDXDL tCVCTV tCVDEX tCHCTV tLHAV tCVCTX tCHAV Data in Setup Data in Hold Status Active Delay Status Inactive Delay Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Invalid to ALE Low(a) AD Address Float Delay DEN Inactive to DT/R Low(a) Control Active Delay DEN Inactive Delay Control Active Delay 2(c) ALE High to Address Valid Control Inactive Delay(b) CLKOUTA High to A Address Valid 1(b) tCLCH tCLAX =0 0 0 0 0 20 0 0 25 25 25 25 25 25 tCLCL -10=40 25 tCLCH tCLAX =0 0 0 0 0 15 0 0 20 20 20 20 20 20 Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 0 0 0 0 25 tCLCL -10=30 20 25 25 25 10 3 0 0 0 0 20 20 20 20
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the INTA1-INTA0 signals. This parameter applies to the DEN and DT/R signals.
78
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Interrupt Acknowledge Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Requirements 1 2 3 4 7 8 9 10 11 12 15 19 20 21 22 23 31 68 tDVCL tCLDX tCHSV tCLSH tCLDV tCHDX tCHLH tLHLL tCHLL tAVLL tCLAZ tDXDL tCVCTV tCVDEX tCHCTV tLHAV tCVCTX tCHAV Data in Setup Data in Hold Status Active Delay Status Inactive Delay Data Valid Delay Status Hold Time ALE Active Delay ALE Width ALE Inactive Delay AD Address Invalid to ALE Low(a) AD Address Float Delay DEN Inactive to DT/R Low(a) Control Active Delay DEN Inactive Delay Control Active Delay 2(c) ALE High to Address Valid Control Inactive Delay(b) CLKOUTA High to A Address Valid 1(b) tCLCH tCLAX =0 0 0 0 0 10 0 0 15 15 15 15 15 15 tCLCL -10=20 15 tCLCH tCLAX =0 0 0 0 0 7.5 0 0 12 10 12 12 12 12 Preliminary 33 MHz 40 MHz Min Max Min Max 8 3 0 0 0 0 15 tCLCL -5=20 12 15 15 15 5 2 0 0 0 0 12 12 12 12
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
General Timing Responses
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b c Equal loading on referenced pins. This parameter applies to the INTA1-INTA0 signals. This parameter applies to the DEN and DT/R signals.
Am186/188EM and Am186/188EMLV Microcontrollers
79
PRELIMINARY
Interrupt Acknowledge Cycle Waveforms
t1 t2 t3 tW CLKOUTA
68
t4
A19-A0
7
Address
8
S6 AD15-AD0*, AD7-AD0**
S6
1 12
S6
2 (b)
Ptr
15
AO15-AO8**
9
Address
23 10 11
ALE
BHE*
BHE
31
INTA1-INTA0
20
DEN
22 19 (c) 22 21
DT/R
3 4 (a) 22 (d)
S2-S0
Status
Notes:
* **
Am186EM microcontroller only AM188EM microcontroller only
a The status bits become inactive in the state preceding t4. b The data hold time lasts only until the interrupt acknowledge signal deasserts, even if the interrupt acknowledge transition occurs prior to tCLDX (min). c This parameter applies for an interrupt acknowledge cycle that follows a write cycle. d If followed by a write cycle, this change occurs in the state preceding that write cycle.
80
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Software Halt Cycle (20 MHz and 25 MHz)
Parameter No. Symbol Description General Timing Responses 3 4 5 9 10 11 19 22 68 tCHSV tCLSH tCLAV tCHLH tLHLL tCHLL tDXDL tCHCTV tCHAV Status Active Delay Status Inactive Delay AD Address Invalid Delay and BHE ALE Active Delay ALE Width ALE Inactive Delay DEN Inactive to DT/R Low Control Active Delay 2(b) CLKOUTA High to A Address Invalid
(a)
Preliminary 20 MHz 25 MHz Min Max Min Max 0 0 0 25 25 25 25 tCLCL -10=40 25 0 0 0 25 25 0 0 0 20 20 tCLCL -10=30 20 0 0 0 20 20 20 20
Unit ns ns ns ns ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. This parameter applies to the DEN signal.
Am186/188EM and Am186/188EMLV Microcontrollers
81
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Software Halt Cycle (33 MHz and 40 MHz)
Parameter No. Symbol Description General Timing Responses 3 4 5 9 10 11 19 22 68 tCHSV tCLSH tCLAV tCHLH tLHLL tCHLL tDXDL tCHCTV tCHAV Status Active Delay Status Inactive Delay AD Address Invalid Delay and BHE ALE Active Delay ALE Width ALE Inactive Delay DEN Inactive to DT/R Low Control Active Delay 2(b) CLKOUTA High to A Address Invalid
(a)
Preliminary 33 MHz 40 MHz Min Max Min Max 0 0 0 15 15 15 15 tCLCL -10=20 15 0 0 0 15 15 0 0 0 12 10 tCLCL -5=20 12 0 0 0 12 12 12 12
Unit ns ns ns ns ns ns ns ns ns
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b Equal loading on referenced pins. This parameter applies to the DEN signal.
82
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Software Halt Cycle Waveforms
t1 t2 ti ti
CLKOUTA
68
A19-A0
5
Invalid Address
S6, AD15-AD0*, AD7-AD0**, AO15-AO8** ALE
9
Invalid Address
10
11
DEN
19
DT/R
22 4
S2-S0
3
Status
Notes:
* **
Am186EM microcontroller only AM188EM microcontroller only
Am186/188EM and Am186/188EMLV Microcontrollers
83
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Clock (20 MHZ and 25 MHz)
Parameter No. Symbol Description CLKIN Requirements 36 37 38 39 40 42 43 44 45 46 61 69 70 tCKIN tCLCK tCHCK tCKHL tCKLH tCLCL tCLCH X1 Period(a) X1 Low Time (1.5 V)(a) X1 High Time (1.5 V)
(a)
Preliminary 20 MHz 25 MHz Min Max Min Max 50 15 15 V)(a) 5 5 50 0.5tCLCL -2 =23 0.5tCLCL -2 =23 3 3 1 15 21 40 0.5tCLCL -2 =18 0.5tCLCL -2 =18 3 3 1 15 21 60 40 15 15 5 5 60
Unit ns ns ns ns ns ns ns ns ns ns ms ns ns
X1 Fall Time (3.5 to 1.0
X1 Rise Time (1.0 to 3.5 V)(a) CLKOUTA Period
CLKOUT Timing CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time tCHCL (CL =50 pF) CLKOUTA Rise Time tCH1CH2 (1.0 to 3.5 V) CLKOUTA Fall Time tCL2CL1 (3.5 to 1.0 V) tLOCK tCICOA tCICOB Maximum PLL Lock Time X1 to CLKOUTA Skew X1 to CLKOUTB Skew
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
84
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Clock (33 MHZ and 40 MHz)
Parameter No. Symbol Description CLKIN Requirements 36 37 38 39 40 42 43 44 45 46 61 69 70 tCKIN tCLCK tCHCK tCKHL tCKLH tCLCL tCLCH X1 Period(a) X1 Low Time (1.5 V)(a) X1 High Time (1.5 V)
(a)
Preliminary 33 MHz 40 MHz Min Max Min Max 30 10 10 V)(a) 5 5 30 0.5tCLCL -1.5 =13.5 0.5tCLCL -1.5 =13.5 3 3 1 15 21 25 0.5tCLCL -1.25 =11.25 0.5tCLCL -1.25 =11.25 3 3 1 15 21 60 25 7.5 7.5 5 5 60
Unit ns ns ns ns ns ns ns ns ns ns ms ns ns
X1 Fall Time (3.5 to 1.0
X1 Rise Time (1.0 to 3.5 V)(a) CLKOUTA Period
CLKOUT Timing CLKOUTA Low Time (CL =50 pF) CLKOUTA High Time tCHCL (CL =50 pF) CLKOUTA Rise Time tCH1CH2 (1.0 to 3.5 V) CLKOUTA Fall Time tCL2CL1 (3.5 to 1.0 V) tLOCK tCICOA tCICOB Maximum PLL Lock Time X1 to CLKOUTA Skew X1 to CLKOUTB Skew
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation.
Am186/188EM and Am186/188EMLV Microcontrollers
85
PRELIMINARY
Clock Waveforms--Active Mode
X2
36 37 38
X1
39 40 45 46
CLKOUTA (Active, F=000)
69 42 43 44
CLKOUTB
70
Clock Waveforms--Power-Save Mode
X2
X1 CLKOUTA(a)
CLKOUTB(b)
CLKOUTB(c)
Notes: a The Clock Divisor Select (F2-F0) bits in the Power Save Control Register (PDCON) are set to 010 (divide by 4). b c The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 1. The CLKOUTB Output Frequency (CBF) bit in the Power Save Control Register (PDCON) is set to 0.
86
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Ready and Peripheral Timing (20 MHz and 25 MHz)
Parameter No. Symbol Description Ready and Peripheral Timing Requirements 47 48 49 50 51 52 53 54 55 tSRYCL tCLSRY tARYCH tCLARX tARYCHL tARYLCL tINVCH tINVCL tCLTMV SRDY Transition Setup Time(a) SRDY Transition Hold Time(a) ARDY Resolution Transition Setup Time(b) ARDY Active Hold Time(a) ARDY Inactive Holding Time ARDY Setup Time(a) Peripheral Setup Time DRQ Setup Time(b) Timer Output Delay
(b)
Preliminary 20 MHz Min Max 10 3 10 4 6 15 10 10 25
Preliminary 25 MHz Min Max 10 3 10 4 6 15 10 10 20
Unit ns ns ns ns ns ns ns ns ns
Peripheral Timing Responses
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b This timing must be met to guarantee proper operation. This timing must be met to guarantee recognition at the clock edge.
Am186/188EM and Am186/188EMLV Microcontrollers
87
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Ready and Peripheral Timing (33 MHz and 40 MHz)
Parameter No. Symbol Description Ready and Peripheral Timing Requirements 47 48 49 50 51 52 53 54 55 tSRYCL tCLSRY tARYCH tCLARX tARYLCL tINVCH tINVCL tCLTMV SRDY Transition Setup Time(a) SRDY Transition Hold Time(a) ARDY Resolution Transition Setup Time(b) ARDY Active Hold Time(a) ARDY Setup Time(a) Peripheral Setup Time DRQ Setup Time(b) Timer Output Delay
(b)
Preliminary 33 MHz 40 MHz Min Max Min Max 8 3 8 4 6 10 8 8 15 5 2 5 3 5 5 5 5 12
Unit ns ns ns ns ns ns ns ns ns
tARYCHL ARDY Inactive Holding Time
Peripheral Timing Responses
Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a b This timing must be met to guarantee proper operation. This timing must be met to guarantee recognition at the clock edge.
Synchronous Ready Waveforms
Case 1 Case 2 Case 3 Case 4
tW t3 t2 t1
tW tW t3 t2
tW tW tW t3
t4 t4 t4 t4
CLKOUTA
47
SRDY
48
88
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Asynchronous Ready Waveforms
Case 1 Case 2 Case 3 Case 4 tW t3 t2 t1 tW tW t3 t2 tW tW tW t3 t4 t4 t4 t4
CLKOUTA
49 50
ARDY (Normally NotReady System)
49
ARDY (Normally Ready System)
51
50
52
Peripheral Waveforms
CLKOUTA
53
INT4-INT0, NMI, TMRIN1-TMRIN0
54
DRQ1-DRQ0
55
TMROUT1- TMROUT0
Am186/188EM and Am186/188EMLV Microcontrollers
89
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Reset and Bus Hold (20 MHz and 25 MHz)
Parameter No. Symbol Description Reset and Bus Hold Timing Requirements 5 15 57 58 62 63 64 tCLAV tCLAZ tRESIN tHVCL tCLHAV tCHCZ tCHCV AD Address Valid Delay and BHE AD Address Float Delay RES Setup Time HOLD Setup(a) Preliminary 20 MHz 25 MHz Min Max Min Max 0 0 10 10 0 25 25 25 25 25 0 0 10 10 0 20 20 20 20 20
Unit ns ns ns ns ns ns ns
Reset and Bus Hold Timing Responses HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float)
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a This timing must be met to guarantee recognition at the next clock.
Reset and Bus Hold (33 MHz and 40 MHz)
Parameter No. Symbol Description Reset and Bus Hold Timing Requirements 5 15 57 58 62 63 64 tCLAV tCLAZ tRESIN tHVCL tCLHAV tCHCZ tCHCV AD Address Valid Delay and BHE AD Address Float Delay RES Setup Time HOLD Setup(a) Preliminary 33 MHz 40 MHz Min Max Min Max 0 0 8 8 0 15 15 15 15 15 0 0 5 5 0 12 12 12 12 12
Unit ns ns ns ns ns ns ns
Reset and Bus Hold Timing Responses HLDA Valid Delay Command Lines Float Delay Command Lines Valid Delay (after Float)
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V. a This timing must be met to guarantee recognition at the next clock.
90
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
Reset Waveforms
X1
57 57
RES
CLKOUTA
Signals Related to Reset Waveforms
RES
CLKOUTA
BHE/ADEN, RFSH2/ADEN, S6/CLKDIV2, and UZI
three-state
AD15-AD0 (186) AO15-AO8, AD7-AD0 (188)
three-state
Am186/188EM and Am186/188EMLV Microcontrollers
91
PRELIMINARY
Bus Hold Waveforms--Entering
Case 1 Case 2 ti t4 ti ti ti ti
CLKOUTA
58
HOLD
62
HLDA
15
AD15-AD0, DEN A19-A0, S6, RD, WR, BHE, DT/R, S2-S0 WHB, WLB
63
Bus Hold Waveforms--Leaving
Case 1 Case 2 ti ti ti ti ti t4 t1 t1
CLKOUTA
58
HOLD
62
HLDA
5
AD15-AD0, DEN
64
A19-A0, S6, RD, WR, BHE, DT/R, S2-S0 WHB, WLB
92
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
SWITCHING CHARACTERISTICS over COMMERCIAL operating range Synchronous Serial Interface (SSI) (20 MHz and 25 MHz)
Parameter No. Symbol Description Synchronous Serial Port Timing Requirements 75 77 71 72 78 tDVSH tSHDX tCLEV tCLSL tSLDV Data Valid to SCLK High SCLK High to SPI Data Hold CLKOUTA Low to SDEN Valid CLKOUTA Low to SCLK Low SCLK Low to Data Valid Preliminary 20 MHz 25 MHz Min Max Min Max 10 3 25 25 25 10 3 20 20 20
Unit ns ns ns ns ns
Synchronous Serial Port Timing Responses
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V.
Synchronous Serial Interface (SSI) (33 MHz and 40 MHz)
Parameter No. Symbol Description Synchronous Serial Port Timing Requirements 75 77 71 72 78 tDVSH tSHDX tCLEV tCLSL tSLDV Data Valid to SCLK High SCLK High to SPI Data Hold CLKOUTA Low to SDEN Valid CLKOUTA Low to SCLK Low SCLK Low to Data Valid Preliminary 33 MHz 40 MHz Min Max Min Max 8 2 0 0 0 15 15 15 5 2 0 0 0 12 12 12
Unit ns ns ns ns ns
Synchronous Serial Port Timing Responses
Note: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA unless otherwise noted. All output test conditions are with CL = 50 pF. For switching tests, VIL = 0.45 V and VIH = 2.4 V, except at X1 where VIH = VCC - 0.5 V.
Am186/188EM and Am186/188EMLV Microcontrollers
93
PRELIMINARY
Synchronous Serial Interface (SSI) Waveforms
CLKOUTA
71
SDEN
72 72
SCLK
SDATA (RX)
75
DATA
77
SDATA (TX)
78
DATA
Note: SDATA is bidirectional and used for either transmit (TX) or receive (RX). Timing is shown separately for each case.
94
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
TQFP PHYSICAL DIMENSIONS PQL 100, Trimmed and Formed Thin Quad Flat Pack
Pin 100
Pin 75 Pin 1 ID
12.00 Ref
-A-
-B-
13.80 14.20 15.80 16.20
Pin 25
-D-
12.00 Ref 13.80 14.20 15.80 16.20 Top View See Detail X
Pin 50
1.35 1.45 S 0.50 Basic 1.00 Ref Side View
S
1.60 Max
-A- -C-
Seating Plane
Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale; for reference only.
pql100 4-15-94
Am186/188EM and Am186/188EMLV Microcontrollers
95
PRELIMINARY
PQL 100 (continued)
0 Min 1.60 Max Gage Plane 0.13 R 0.20 0.05 0.15
0.25 0-7 0.17 0.27
Seating Plane 0.45 0.75 0.20 Max 0.08 Lead Coplanarity
Detail X
0.17 0.27
0.14 0.18
Section S-S
Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale; for reference only.
pql100 4-15-94
96
Am186/188EM and Am186/188EMLV Microcontrollers
PRELIMINARY
PQFP PHYSICAL DIMENSIONS PQR 100, Trimmed and Formed Plastic Quad Flat Pack
17.00 17.40 13.90 14.10 12.35 REF Pin 80
Pin 100
Pin 1 I.D.
18.85 REF --A-
-B-
19.90 20.10 23.00 23.40
Pin 30 - -D-
Pin 50
Top View
See Detail X 0.65 BASIC 2.70 2.90 0.25 Min S S 3.35 Max
-A-
Seating
-C- Side View
Notes: 1. All measurements are in millimeters unless otherwise noted. 2. Not to scale; for reference only.
pqr100 4-15-94
Am186/188EM and Am186/188EMLV Microcontrollers
97
PRELIMINARY
PQFP PQR 100 (continued)
0.20 Min. Flat Shoulder 7 Typ.
0 Min. 0.300.05 R 3.35 Max
Gage Plane
0.25 0.73 1.03 0-7 7 Typ. 0.22 0.38 0.15 0.23
Detail X
0.22 0.38
0.15 0.23
Section S-S
Note: Not to scale; for reference only.
pqr100 4-15-94
Trademarks AMD, the AMD logo, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Am386 and Am486 are registered trademarks of Advanced Micro Devices, Inc. Am186, Am188, E86, K86, Elan, and AMD Facts-On-Demand are trademarks of Advanced Micro Devices, Inc. FusionE86 is a service mark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
98
Am186/188EM and Am186/188EMLV Microcontrollers

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